[2025-09-21T08:11:14Z INFO snow_core::mac::compact::bus] Skipping memory test [2025-09-21T08:11:14Z INFO snow_core::cpu_m68k::cpu] Reset - SSP: 4D1F8172, PC: 0040002A [2025-09-21T08:11:14Z INFO single] No replay file found [2025-09-21T08:11:14Z INFO single] Starting [2025-09-21T08:11:14Z INFO single] Event: Status: EmulatorStatus { regs: RegisterFile { d: [0, 0, 0, 0, 0, 0, 0, 0], a: [0, 0, 0, 0, 0, 0, 0], usp: 0, isp: 1293910386, sr: RegisterSR { 0: 9984, sr: 9984, ccr: 0, c: false, v: false, z: false, n: false, x: false, int_prio_mask: 7, m: false, supervisor: true, trace: false }, pc: 4194346, dfc: 0, sfc: 0, vbr: 0, caar: 0, cacr: RegisterCACR { 0: 0, e: false, f: false, ce: false, c: false }, msp: 0, fpu: FpuRegisterFile { fp: [Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }], fpcr: RegisterFPCR { 0: 0, mode: 0, rnd: 0, prec: 0, exc: FpuExceptions { 0: 0, inex1: false, inex2: false, dz: false, unfl: false, ovfl: false, operr: false, snan: false, bsun: false } }, fpsr: RegisterFPSR { 0: 0, fpcc: 0, fpcc_nan: false, fpcc_i: false, fpcc_z: false, fpcc_n: false, quotient: 0, quotient_s: false, exs: FpuExceptions { 0: 0, inex1: false, inex2: false, dz: false, unfl: false, ovfl: false, operr: false, snan: false, bsun: false }, aexc: FpuAccruedExceptions { 0: 0, inex: false, dz: false, unfl: false, ovfl: false, iop: false, snan: false, bsun: false } }, fpiar: 0 }, pmmu: PmmuRegisterFile { crp: RootPointerReg { 0: 0, lu: false, limit: 0, sg: false, dt: 0, table_addr: 0 }, srp: RootPointerReg { 0: 0, lu: false, limit: 0, sg: false, dt: 0, table_addr: 0 }, drp: RootPointerReg { 0: 0, lu: false, limit: 0, sg: false, dt: 0, table_addr: 0 }, pcsr: RegisterPCSR { 0: 0, ta: 0, flush: false, lw: false }, cal: AccessLevelReg { 0: 0, al: 0 }, val: AccessLevelReg { 0: 0, al: 0 }, scc: 0, ac: AccessControlReg { 0: 0, mc: false, alc: 0, mds: 0 }, tc: TcReg { 0: 0, enable: false, sre: false, fcl: false, ps: 0, is: 0, tia: 0, tib: 0, tic: 0, tid: 0 }, psr: RegisterPSR { 0: 0, bus_error: false, limit_violation: false, supervisor_violation: false, access_level_violatiom: false, write_protected: false, invalid: false, modified: false, gate: false, globally_shared: false, level_number: 0 }, last_desc: 0 } }, running: false, breakpoints: [], cycles: 24, fdd: [FddStatus { present: true, ejected: true, motor: false, writing: false, track: 4, image_title: "", dirty: false }, FddStatus { present: true, ejected: true, motor: false, writing: false, track: 4, image_title: "", dirty: false }, FddStatus { present: false, ejected: true, motor: false, writing: false, track: 4, image_title: "", dirty: false }], model: Plus, speed: Accurate, scsi: [None, None, None, None, None, None, None] } [2025-09-21T08:11:14Z INFO single] Event: NextCode [2025-09-21T08:11:14Z INFO snow_core::mac::swim::drive] Drive 0: disk inserted, 80 tracks, title: 'Dark Castle' [2025-09-21T08:11:14Z INFO snow_core::emulator] Running [2025-09-21T08:11:14Z INFO snow_core::mac::compact::bus] Emulation speed: Uncapped [2025-09-21T08:11:14Z INFO single] Event: Status: EmulatorStatus { regs: RegisterFile { d: [0, 0, 0, 0, 0, 0, 0, 0], a: [0, 0, 0, 0, 0, 0, 0], usp: 0, isp: 1293910386, sr: RegisterSR { 0: 9984, sr: 9984, ccr: 0, c: false, v: false, z: false, n: false, x: false, int_prio_mask: 7, m: false, supervisor: true, trace: false }, pc: 4194346, dfc: 0, sfc: 0, vbr: 0, caar: 0, cacr: RegisterCACR { 0: 0, e: false, f: false, ce: false, c: false }, msp: 0, fpu: FpuRegisterFile { fp: [Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }], fpcr: RegisterFPCR { 0: 0, mode: 0, rnd: 0, prec: 0, exc: FpuExceptions { 0: 0, inex1: false, inex2: false, dz: false, unfl: false, ovfl: false, operr: false, snan: false, bsun: false } }, fpsr: RegisterFPSR { 0: 0, fpcc: 0, fpcc_nan: false, fpcc_i: false, fpcc_z: false, fpcc_n: false, quotient: 0, quotient_s: false, exs: FpuExceptions { 0: 0, inex1: false, inex2: false, dz: false, unfl: false, ovfl: false, operr: false, snan: false, bsun: false }, aexc: FpuAccruedExceptions { 0: 0, inex: false, dz: false, unfl: false, ovfl: false, iop: false, snan: false, bsun: false } }, fpiar: 0 }, pmmu: PmmuRegisterFile { crp: RootPointerReg { 0: 0, lu: false, limit: 0, sg: false, dt: 0, table_addr: 0 }, srp: RootPointerReg { 0: 0, lu: false, limit: 0, sg: false, dt: 0, table_addr: 0 }, drp: RootPointerReg { 0: 0, lu: false, limit: 0, sg: false, dt: 0, table_addr: 0 }, pcsr: RegisterPCSR { 0: 0, ta: 0, flush: false, lw: false }, cal: AccessLevelReg { 0: 0, al: 0 }, val: AccessLevelReg { 0: 0, al: 0 }, scc: 0, ac: AccessControlReg { 0: 0, mc: false, alc: 0, mds: 0 }, tc: TcReg { 0: 0, enable: false, sre: false, fcl: false, ps: 0, is: 0, tia: 0, tib: 0, tic: 0, tid: 0 }, psr: RegisterPSR { 0: 0, bus_error: false, limit_violation: false, supervisor_violation: false, access_level_violatiom: false, write_protected: false, invalid: false, modified: false, gate: false, globally_shared: false, level_number: 0 }, last_desc: 0 } }, running: false, breakpoints: [], cycles: 24, fdd: [FddStatus { present: true, ejected: false, motor: false, writing: false, track: 4, image_title: "Dark Castle", dirty: false }, FddStatus { present: true, ejected: true, motor: false, writing: false, track: 4, image_title: "", dirty: false }, FddStatus { present: false, ejected: true, motor: false, writing: false, track: 4, image_title: "", dirty: false }], model: Plus, speed: Accurate, scsi: [None, None, None, None, None, None, None] } [2025-09-21T08:11:14Z INFO single] Event: NextCode [2025-09-21T08:11:14Z INFO single] Event: Status: EmulatorStatus { regs: RegisterFile { d: [0, 0, 0, 0, 0, 0, 0, 0], a: [0, 0, 0, 0, 0, 0, 0], usp: 0, isp: 1293910386, sr: RegisterSR { 0: 9984, sr: 9984, ccr: 0, c: false, v: false, z: false, n: false, x: false, int_prio_mask: 7, m: false, supervisor: true, trace: false }, pc: 4194346, dfc: 0, sfc: 0, vbr: 0, caar: 0, cacr: RegisterCACR { 0: 0, e: false, f: false, ce: false, c: false }, msp: 0, fpu: FpuRegisterFile { fp: [Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }], fpcr: RegisterFPCR { 0: 0, mode: 0, rnd: 0, prec: 0, exc: FpuExceptions { 0: 0, inex1: false, inex2: false, dz: false, unfl: false, ovfl: false, operr: false, snan: false, bsun: false } }, fpsr: RegisterFPSR { 0: 0, fpcc: 0, fpcc_nan: false, fpcc_i: false, fpcc_z: false, fpcc_n: false, quotient: 0, quotient_s: false, exs: FpuExceptions { 0: 0, inex1: false, inex2: false, dz: false, unfl: false, ovfl: false, operr: false, snan: false, bsun: false }, aexc: FpuAccruedExceptions { 0: 0, inex: false, dz: false, unfl: false, ovfl: false, iop: false, snan: false, bsun: false } }, fpiar: 0 }, pmmu: PmmuRegisterFile { crp: RootPointerReg { 0: 0, lu: false, limit: 0, sg: false, dt: 0, table_addr: 0 }, srp: RootPointerReg { 0: 0, lu: false, limit: 0, sg: false, dt: 0, table_addr: 0 }, drp: RootPointerReg { 0: 0, lu: false, limit: 0, sg: false, dt: 0, table_addr: 0 }, pcsr: RegisterPCSR { 0: 0, ta: 0, flush: false, lw: false }, cal: AccessLevelReg { 0: 0, al: 0 }, val: AccessLevelReg { 0: 0, al: 0 }, scc: 0, ac: AccessControlReg { 0: 0, mc: false, alc: 0, mds: 0 }, tc: TcReg { 0: 0, enable: false, sre: false, fcl: false, ps: 0, is: 0, tia: 0, tib: 0, tic: 0, tid: 0 }, psr: RegisterPSR { 0: 0, bus_error: false, limit_violation: false, supervisor_violation: false, access_level_violatiom: false, write_protected: false, invalid: false, modified: false, gate: false, globally_shared: false, level_number: 0 }, last_desc: 0 } }, running: true, breakpoints: [], cycles: 24, fdd: [FddStatus { present: true, ejected: false, motor: false, writing: false, track: 4, image_title: "Dark Castle", dirty: false }, FddStatus { present: true, ejected: true, motor: false, writing: false, track: 4, image_title: "", dirty: false }, FddStatus { present: false, ejected: true, motor: false, writing: false, track: 4, image_title: "", dirty: false }], model: Plus, speed: Accurate, scsi: [None, None, None, None, None, None, None] } [2025-09-21T08:11:14Z INFO single] Event: NextCode [2025-09-21T08:11:14Z INFO single] Event: Status: EmulatorStatus { regs: RegisterFile { d: [43123, 904499564, 20687, 1293910386, 7, 1792, 240, 1], a: [4284002, 4193830, 4193408, 0, 1, 15720958, 4194610], usp: 0, isp: 1293910386, sr: RegisterSR { 0: 9984, sr: 9984, ccr: 0, c: false, v: false, z: false, n: false, x: false, int_prio_mask: 7, m: false, supervisor: true, trace: false }, pc: 4197774, dfc: 0, sfc: 0, vbr: 0, caar: 0, cacr: RegisterCACR { 0: 0, e: false, f: false, ce: false, c: false }, msp: 0, fpu: FpuRegisterFile { fp: [Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }], fpcr: RegisterFPCR { 0: 0, mode: 0, rnd: 0, prec: 0, exc: FpuExceptions { 0: 0, inex1: false, inex2: false, dz: false, unfl: false, ovfl: false, operr: false, snan: false, bsun: false } }, fpsr: RegisterFPSR { 0: 0, fpcc: 0, fpcc_nan: false, fpcc_i: false, fpcc_z: false, fpcc_n: false, quotient: 0, quotient_s: false, exs: FpuExceptions { 0: 0, inex1: false, inex2: false, dz: false, unfl: false, ovfl: false, operr: false, snan: false, bsun: false }, aexc: FpuAccruedExceptions { 0: 0, inex: false, dz: false, unfl: false, ovfl: false, iop: false, snan: false, bsun: false } }, fpiar: 0 }, pmmu: PmmuRegisterFile { crp: RootPointerReg { 0: 0, lu: false, limit: 0, sg: false, dt: 0, table_addr: 0 }, srp: RootPointerReg { 0: 0, lu: false, limit: 0, sg: false, dt: 0, table_addr: 0 }, drp: RootPointerReg { 0: 0, lu: false, limit: 0, sg: false, dt: 0, table_addr: 0 }, pcsr: RegisterPCSR { 0: 0, ta: 0, flush: false, lw: false }, cal: AccessLevelReg { 0: 0, al: 0 }, val: AccessLevelReg { 0: 0, al: 0 }, scc: 0, ac: AccessControlReg { 0: 0, mc: false, alc: 0, mds: 0 }, tc: TcReg { 0: 0, enable: false, sre: false, fcl: false, ps: 0, is: 0, tia: 0, tib: 0, tic: 0, tid: 0 }, psr: RegisterPSR { 0: 0, bus_error: false, limit_violation: false, supervisor_violation: false, access_level_violatiom: false, write_protected: false, invalid: false, modified: false, gate: false, globally_shared: false, level_number: 0 }, last_desc: 0 } }, running: true, breakpoints: [], cycles: 6776346, fdd: [FddStatus { present: true, ejected: false, motor: false, writing: false, track: 4, image_title: "Dark Castle", dirty: false }, FddStatus { present: true, ejected: true, motor: false, writing: false, track: 4, image_title: "", dirty: false }, FddStatus { present: false, ejected: true, motor: false, writing: false, track: 4, image_title: "", dirty: false }], model: Plus, speed: Uncapped, scsi: [None, None, None, None, None, None, None] } [2025-09-21T08:11:14Z INFO single] Event: NextCode [2025-09-21T08:11:15Z INFO single] Event: Status: EmulatorStatus { regs: RegisterFile { d: [829481, 4294967295, 9, 8, 7, 1792, 240, 1], a: [876380, 4194304, 4194304, 0, 3, 4194304, 4194610], usp: 0, isp: 1293910386, sr: RegisterSR { 0: 9984, sr: 9984, ccr: 0, c: false, v: false, z: false, n: false, x: false, int_prio_mask: 7, m: false, supervisor: true, trace: false }, pc: 4195162, dfc: 0, sfc: 0, vbr: 0, caar: 0, cacr: RegisterCACR { 0: 0, e: false, f: false, ce: false, c: false }, msp: 0, fpu: FpuRegisterFile { fp: [Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }], fpcr: RegisterFPCR { 0: 0, mode: 0, rnd: 0, prec: 0, exc: FpuExceptions { 0: 0, inex1: false, inex2: false, dz: false, unfl: false, ovfl: false, operr: false, snan: false, bsun: false } }, fpsr: RegisterFPSR { 0: 0, fpcc: 0, fpcc_nan: false, fpcc_i: false, fpcc_z: false, fpcc_n: false, quotient: 0, quotient_s: false, exs: FpuExceptions { 0: 0, inex1: false, inex2: false, dz: false, unfl: false, ovfl: false, operr: false, snan: false, bsun: false }, aexc: FpuAccruedExceptions { 0: 0, inex: false, dz: false, unfl: false, ovfl: false, iop: false, snan: false, bsun: false } }, fpiar: 0 }, pmmu: PmmuRegisterFile { crp: RootPointerReg { 0: 0, lu: false, limit: 0, sg: false, dt: 0, table_addr: 0 }, srp: RootPointerReg { 0: 0, lu: false, limit: 0, sg: false, dt: 0, table_addr: 0 }, drp: RootPointerReg { 0: 0, lu: false, limit: 0, sg: false, dt: 0, table_addr: 0 }, pcsr: RegisterPCSR { 0: 0, ta: 0, flush: false, lw: false }, cal: AccessLevelReg { 0: 0, al: 0 }, val: AccessLevelReg { 0: 0, al: 0 }, scc: 0, ac: AccessControlReg { 0: 0, mc: false, alc: 0, mds: 0 }, tc: TcReg { 0: 0, enable: false, sre: false, fcl: false, ps: 0, is: 0, tia: 0, tib: 0, tic: 0, tid: 0 }, psr: RegisterPSR { 0: 0, bus_error: false, limit_violation: false, supervisor_violation: false, access_level_violatiom: false, write_protected: false, invalid: false, modified: false, gate: false, globally_shared: false, level_number: 0 }, last_desc: 0 } }, running: true, breakpoints: [], cycles: 14738126, fdd: [FddStatus { present: true, ejected: false, motor: false, writing: false, track: 4, image_title: "Dark Castle", dirty: false }, FddStatus { present: true, ejected: true, motor: false, writing: false, track: 4, image_title: "", dirty: false }, FddStatus { present: false, ejected: true, motor: false, writing: false, track: 4, image_title: "", dirty: false }], model: Plus, speed: Uncapped, scsi: [None, None, None, None, None, None, None] } [2025-09-21T08:11:15Z INFO single] Event: NextCode [2025-09-21T08:11:15Z INFO single] Event: Status: EmulatorStatus { regs: RegisterFile { d: [592814, 4294967295, 9, 8, 7, 1792, 240, 1], a: [1823048, 4194304, 4194304, 0, 3, 4194304, 4194610], usp: 0, isp: 1293910386, sr: RegisterSR { 0: 9984, sr: 9984, ccr: 0, c: false, v: false, z: false, n: false, x: false, int_prio_mask: 7, m: false, supervisor: true, trace: false }, pc: 4195166, dfc: 0, sfc: 0, vbr: 0, caar: 0, cacr: RegisterCACR { 0: 0, e: false, f: false, ce: false, c: false }, msp: 0, fpu: FpuRegisterFile { fp: [Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }], fpcr: RegisterFPCR { 0: 0, mode: 0, rnd: 0, prec: 0, exc: FpuExceptions { 0: 0, inex1: false, inex2: false, dz: false, unfl: false, ovfl: false, operr: false, snan: false, bsun: false } }, fpsr: RegisterFPSR { 0: 0, fpcc: 0, fpcc_nan: false, fpcc_i: false, fpcc_z: false, fpcc_n: false, quotient: 0, quotient_s: false, exs: FpuExceptions { 0: 0, inex1: false, inex2: false, dz: false, unfl: false, ovfl: false, operr: false, snan: false, bsun: false }, aexc: FpuAccruedExceptions { 0: 0, inex: false, dz: false, unfl: false, ovfl: false, iop: false, snan: false, bsun: false } }, fpiar: 0 }, pmmu: PmmuRegisterFile { crp: RootPointerReg { 0: 0, lu: false, limit: 0, sg: false, dt: 0, table_addr: 0 }, srp: RootPointerReg { 0: 0, lu: false, limit: 0, sg: false, dt: 0, table_addr: 0 }, drp: RootPointerReg { 0: 0, lu: false, limit: 0, sg: false, dt: 0, table_addr: 0 }, pcsr: RegisterPCSR { 0: 0, ta: 0, flush: false, lw: false }, cal: AccessLevelReg { 0: 0, al: 0 }, val: AccessLevelReg { 0: 0, al: 0 }, scc: 0, ac: AccessControlReg { 0: 0, mc: false, alc: 0, mds: 0 }, tc: TcReg { 0: 0, enable: false, sre: false, fcl: false, ps: 0, is: 0, tia: 0, tib: 0, tic: 0, tid: 0 }, psr: RegisterPSR { 0: 0, bus_error: false, limit_violation: false, supervisor_violation: false, access_level_violatiom: false, write_protected: false, invalid: false, modified: false, gate: false, globally_shared: false, level_number: 0 }, last_desc: 0 } }, running: true, breakpoints: [], cycles: 22752690, fdd: [FddStatus { present: true, ejected: false, motor: false, writing: false, track: 4, image_title: "Dark Castle", dirty: false }, FddStatus { present: true, ejected: true, motor: false, writing: false, track: 4, image_title: "", dirty: false }, FddStatus { present: false, ejected: true, motor: false, writing: false, track: 4, image_title: "", dirty: false }], model: Plus, speed: Uncapped, scsi: [None, None, None, None, None, None, None] } [2025-09-21T08:11:15Z INFO single] Event: NextCode [2025-09-21T08:11:16Z INFO single] Event: Status: EmulatorStatus { regs: RegisterFile { d: [349481, 4294967295, 9, 8, 7, 1792, 240, 1], a: [2796380, 4194304, 4194304, 0, 3, 4194304, 4194610], usp: 0, isp: 1293910386, sr: RegisterSR { 0: 9984, sr: 9984, ccr: 0, c: false, v: false, z: false, n: false, x: false, int_prio_mask: 7, m: false, supervisor: true, trace: false }, pc: 4195162, dfc: 0, sfc: 0, vbr: 0, caar: 0, cacr: RegisterCACR { 0: 0, e: false, f: false, ce: false, c: false }, msp: 0, fpu: FpuRegisterFile { fp: [Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }], fpcr: RegisterFPCR { 0: 0, mode: 0, rnd: 0, prec: 0, exc: FpuExceptions { 0: 0, inex1: false, inex2: false, dz: false, unfl: false, ovfl: false, operr: false, snan: false, bsun: false } }, fpsr: RegisterFPSR { 0: 0, fpcc: 0, fpcc_nan: false, fpcc_i: false, fpcc_z: false, fpcc_n: false, quotient: 0, quotient_s: false, exs: FpuExceptions { 0: 0, inex1: false, inex2: false, dz: false, unfl: false, ovfl: false, operr: false, snan: false, bsun: false }, aexc: FpuAccruedExceptions { 0: 0, inex: false, dz: false, unfl: false, ovfl: false, iop: false, snan: false, bsun: false } }, fpiar: 0 }, pmmu: PmmuRegisterFile { crp: RootPointerReg { 0: 0, lu: false, limit: 0, sg: false, dt: 0, table_addr: 0 }, srp: RootPointerReg { 0: 0, lu: false, limit: 0, sg: false, dt: 0, table_addr: 0 }, drp: RootPointerReg { 0: 0, lu: false, limit: 0, sg: false, dt: 0, table_addr: 0 }, pcsr: RegisterPCSR { 0: 0, ta: 0, flush: false, lw: false }, cal: AccessLevelReg { 0: 0, al: 0 }, val: AccessLevelReg { 0: 0, al: 0 }, scc: 0, ac: AccessControlReg { 0: 0, mc: false, alc: 0, mds: 0 }, tc: TcReg { 0: 0, enable: false, sre: false, fcl: false, ps: 0, is: 0, tia: 0, tib: 0, tic: 0, tid: 0 }, psr: RegisterPSR { 0: 0, bus_error: false, limit_violation: false, supervisor_violation: false, access_level_violatiom: false, write_protected: false, invalid: false, modified: false, gate: false, globally_shared: false, level_number: 0 }, last_desc: 0 } }, running: true, breakpoints: [], cycles: 30992622, fdd: [FddStatus { present: true, ejected: false, motor: false, writing: false, track: 4, image_title: "Dark Castle", dirty: false }, FddStatus { present: true, ejected: true, motor: false, writing: false, track: 4, image_title: "", dirty: false }, FddStatus { present: false, ejected: true, motor: false, writing: false, track: 4, image_title: "", dirty: false }], model: Plus, speed: Uncapped, scsi: [None, None, None, None, None, None, None] } [2025-09-21T08:11:16Z INFO single] Event: NextCode [2025-09-21T08:11:16Z INFO single] Event: Status: EmulatorStatus { regs: RegisterFile { d: [112814, 4294967295, 9, 8, 7, 1792, 240, 1], a: [3743048, 4194304, 4194304, 0, 3, 4194304, 4194610], usp: 0, isp: 1293910386, sr: RegisterSR { 0: 9984, sr: 9984, ccr: 0, c: false, v: false, z: false, n: false, x: false, int_prio_mask: 7, m: false, supervisor: true, trace: false }, pc: 4195166, dfc: 0, sfc: 0, vbr: 0, caar: 0, cacr: RegisterCACR { 0: 0, e: false, f: false, ce: false, c: false }, msp: 0, fpu: FpuRegisterFile { fp: [Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }], fpcr: RegisterFPCR { 0: 0, mode: 0, rnd: 0, prec: 0, exc: FpuExceptions { 0: 0, inex1: false, inex2: false, dz: false, unfl: false, ovfl: false, operr: false, snan: false, bsun: false } }, fpsr: RegisterFPSR { 0: 0, fpcc: 0, fpcc_nan: false, fpcc_i: false, fpcc_z: false, fpcc_n: false, quotient: 0, quotient_s: false, exs: FpuExceptions { 0: 0, inex1: false, inex2: false, dz: false, unfl: false, ovfl: false, operr: false, snan: false, bsun: false }, aexc: FpuAccruedExceptions { 0: 0, inex: false, dz: false, unfl: false, ovfl: false, iop: false, snan: false, bsun: false } }, fpiar: 0 }, pmmu: PmmuRegisterFile { crp: RootPointerReg { 0: 0, lu: false, limit: 0, sg: false, dt: 0, table_addr: 0 }, srp: RootPointerReg { 0: 0, lu: false, limit: 0, sg: false, dt: 0, table_addr: 0 }, drp: RootPointerReg { 0: 0, lu: false, limit: 0, sg: false, dt: 0, table_addr: 0 }, pcsr: RegisterPCSR { 0: 0, ta: 0, flush: false, lw: false }, cal: AccessLevelReg { 0: 0, al: 0 }, val: AccessLevelReg { 0: 0, al: 0 }, scc: 0, ac: AccessControlReg { 0: 0, mc: false, alc: 0, mds: 0 }, tc: TcReg { 0: 0, enable: false, sre: false, fcl: false, ps: 0, is: 0, tia: 0, tib: 0, tic: 0, tid: 0 }, psr: RegisterPSR { 0: 0, bus_error: false, limit_violation: false, supervisor_violation: false, access_level_violatiom: false, write_protected: false, invalid: false, modified: false, gate: false, globally_shared: false, level_number: 0 }, last_desc: 0 } }, running: true, breakpoints: [], cycles: 39005798, fdd: [FddStatus { present: true, ejected: false, motor: false, writing: false, track: 4, image_title: "Dark Castle", dirty: false }, FddStatus { present: true, ejected: true, motor: false, writing: false, track: 4, image_title: "", dirty: false }, FddStatus { present: false, ejected: true, motor: false, writing: false, track: 4, image_title: "", dirty: false }], model: Plus, speed: Uncapped, scsi: [None, None, None, None, None, None, None] } [2025-09-21T08:11:16Z INFO single] Event: NextCode [2025-09-21T08:11:16Z DEBUG snow_core::cpu_m68k::cpu] Illegal instruction PC 00400594: 4E7B 0100111001111011 Cannot decode instruction: 0100111001111011 [2025-09-21T08:11:16Z WARN snow_core::cpu_m68k::cpu] Illegal instruction at PC $00400594 [2025-09-21T08:11:17Z WARN snow_core::mac::scc] B unimplemented wr reg 4 4C [2025-09-21T08:11:17Z WARN snow_core::mac::scc] A unimplemented wr reg 4 4C [2025-09-21T08:11:17Z INFO snow_core::mac::pluskbd] Keyboard reset [2025-09-21T08:11:17Z INFO single] Event: Status: EmulatorStatus { regs: RegisterFile { d: [4216149, 4294967295, 2, 0, 31, 0, 1431655765, 157], a: [4228152, 4181628, 2095688, 2095998, 4228824, 2096640, 2096070], usp: 0, isp: 2095624, sr: RegisterSR { 0: 8192, sr: 8192, ccr: 0, c: false, v: false, z: false, n: false, x: false, int_prio_mask: 0, m: false, supervisor: true, trace: false }, pc: 4228806, dfc: 0, sfc: 0, vbr: 0, caar: 0, cacr: RegisterCACR { 0: 0, e: false, f: false, ce: false, c: false }, msp: 0, fpu: FpuRegisterFile { fp: [Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }], fpcr: RegisterFPCR { 0: 0, mode: 0, rnd: 0, prec: 0, exc: FpuExceptions { 0: 0, inex1: false, inex2: false, dz: false, unfl: false, ovfl: false, operr: false, snan: false, bsun: false } }, fpsr: RegisterFPSR { 0: 0, fpcc: 0, fpcc_nan: false, fpcc_i: false, fpcc_z: false, fpcc_n: false, quotient: 0, quotient_s: false, exs: FpuExceptions { 0: 0, inex1: false, inex2: false, dz: false, unfl: false, ovfl: false, operr: false, snan: false, bsun: false }, aexc: FpuAccruedExceptions { 0: 0, inex: false, dz: false, unfl: false, ovfl: false, iop: false, snan: false, bsun: false } }, fpiar: 0 }, pmmu: PmmuRegisterFile { crp: RootPointerReg { 0: 0, lu: false, limit: 0, sg: false, dt: 0, table_addr: 0 }, srp: RootPointerReg { 0: 0, lu: false, limit: 0, sg: false, dt: 0, table_addr: 0 }, drp: RootPointerReg { 0: 0, lu: false, limit: 0, sg: false, dt: 0, table_addr: 0 }, pcsr: RegisterPCSR { 0: 0, ta: 0, flush: false, lw: false }, cal: AccessLevelReg { 0: 0, al: 0 }, val: AccessLevelReg { 0: 0, al: 0 }, scc: 0, ac: AccessControlReg { 0: 0, mc: false, alc: 0, mds: 0 }, tc: TcReg { 0: 0, enable: false, sre: false, fcl: false, ps: 0, is: 0, tia: 0, tib: 0, tic: 0, tid: 0 }, psr: RegisterPSR { 0: 0, bus_error: false, limit_violation: false, supervisor_violation: false, access_level_violatiom: false, write_protected: false, invalid: false, modified: false, gate: false, globally_shared: false, level_number: 0 }, last_desc: 0 } }, running: true, breakpoints: [], cycles: 46503776, fdd: [FddStatus { present: true, ejected: false, motor: false, writing: false, track: 4, image_title: "Dark Castle", dirty: false }, FddStatus { present: true, ejected: true, motor: false, writing: false, track: 4, image_title: "", dirty: false }, FddStatus { present: false, ejected: true, motor: false, writing: false, track: 4, image_title: "", dirty: false }], model: Plus, speed: Uncapped, scsi: [None, None, None, None, None, None, None] } [2025-09-21T08:11:17Z INFO single] Event: NextCode [2025-09-21T08:11:17Z INFO single] Event: Status: EmulatorStatus { regs: RegisterFile { d: [1, 74, 2147484398, 1, 0, 1792, 6178, 4198394], a: [2096128, 2147489698, 4203454, 0, 4198424, 2096528, 2097152], usp: 0, isp: 2096096, sr: RegisterSR { 0: 8192, sr: 8192, ccr: 0, c: false, v: false, z: false, n: false, x: false, int_prio_mask: 0, m: false, supervisor: true, trace: false }, pc: 4203552, dfc: 0, sfc: 0, vbr: 0, caar: 0, cacr: RegisterCACR { 0: 0, e: false, f: false, ce: false, c: false }, msp: 0, fpu: FpuRegisterFile { fp: [Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }], fpcr: RegisterFPCR { 0: 0, mode: 0, rnd: 0, prec: 0, exc: FpuExceptions { 0: 0, inex1: false, inex2: false, dz: false, unfl: false, ovfl: false, operr: false, snan: false, bsun: false } }, fpsr: RegisterFPSR { 0: 0, fpcc: 0, fpcc_nan: false, fpcc_i: false, fpcc_z: false, fpcc_n: false, quotient: 0, quotient_s: false, exs: FpuExceptions { 0: 0, inex1: false, inex2: false, dz: false, unfl: false, ovfl: false, operr: false, snan: false, bsun: false }, aexc: FpuAccruedExceptions { 0: 0, inex: false, dz: false, unfl: false, ovfl: false, iop: false, snan: false, bsun: false } }, fpiar: 0 }, pmmu: PmmuRegisterFile { crp: RootPointerReg { 0: 0, lu: false, limit: 0, sg: false, dt: 0, table_addr: 0 }, srp: RootPointerReg { 0: 0, lu: false, limit: 0, sg: false, dt: 0, table_addr: 0 }, drp: RootPointerReg { 0: 0, lu: false, limit: 0, sg: false, dt: 0, table_addr: 0 }, pcsr: RegisterPCSR { 0: 0, ta: 0, flush: false, lw: false }, cal: AccessLevelReg { 0: 0, al: 0 }, val: AccessLevelReg { 0: 0, al: 0 }, scc: 0, ac: AccessControlReg { 0: 0, mc: false, alc: 0, mds: 0 }, tc: TcReg { 0: 0, enable: false, sre: false, fcl: false, ps: 0, is: 0, tia: 0, tib: 0, tic: 0, tid: 0 }, psr: RegisterPSR { 0: 0, bus_error: false, limit_violation: false, supervisor_violation: false, access_level_violatiom: false, write_protected: false, invalid: false, modified: false, gate: false, globally_shared: false, level_number: 0 }, last_desc: 0 } }, running: true, breakpoints: [], cycles: 50915486, fdd: [FddStatus { present: true, ejected: false, motor: true, writing: false, track: 0, image_title: "Dark Castle", dirty: false }, FddStatus { present: true, ejected: true, motor: false, writing: false, track: 4, image_title: "", dirty: false }, FddStatus { present: false, ejected: true, motor: false, writing: false, track: 4, image_title: "", dirty: false }], model: Plus, speed: Uncapped, scsi: [None, None, None, None, None, None, None] } [2025-09-21T08:11:17Z INFO single] Event: NextCode [2025-09-21T08:11:18Z INFO single] Event: Status: EmulatorStatus { regs: RegisterFile { d: [4294967232, 250, 9, 203, 4294836335, 84, 161, 32], a: [2097554, 776, 4295899, 4296238, 14678527, 15728638, 10485758], usp: 0, isp: 2095970, sr: RegisterSR { 0: 8968, sr: 8968, ccr: 8, c: false, v: false, z: false, n: true, x: false, int_prio_mask: 3, m: false, supervisor: true, trace: false }, pc: 4296160, dfc: 0, sfc: 0, vbr: 0, caar: 0, cacr: RegisterCACR { 0: 0, e: false, f: false, ce: false, c: false }, msp: 0, fpu: FpuRegisterFile { fp: [Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }], fpcr: RegisterFPCR { 0: 0, mode: 0, rnd: 0, prec: 0, exc: FpuExceptions { 0: 0, inex1: false, inex2: false, dz: false, unfl: false, ovfl: false, operr: false, snan: false, bsun: false } }, fpsr: RegisterFPSR { 0: 0, fpcc: 0, fpcc_nan: false, fpcc_i: false, fpcc_z: false, fpcc_n: false, quotient: 0, quotient_s: false, exs: FpuExceptions { 0: 0, inex1: false, inex2: false, dz: false, unfl: false, ovfl: false, operr: false, snan: false, bsun: false }, aexc: FpuAccruedExceptions { 0: 0, inex: false, dz: false, unfl: false, ovfl: false, iop: false, snan: false, bsun: false } }, fpiar: 0 }, pmmu: PmmuRegisterFile { crp: RootPointerReg { 0: 0, lu: false, limit: 0, sg: false, dt: 0, table_addr: 0 }, srp: RootPointerReg { 0: 0, lu: false, limit: 0, sg: false, dt: 0, table_addr: 0 }, drp: RootPointerReg { 0: 0, lu: false, limit: 0, sg: false, dt: 0, table_addr: 0 }, pcsr: RegisterPCSR { 0: 0, ta: 0, flush: false, lw: false }, cal: AccessLevelReg { 0: 0, al: 0 }, val: AccessLevelReg { 0: 0, al: 0 }, scc: 0, ac: AccessControlReg { 0: 0, mc: false, alc: 0, mds: 0 }, tc: TcReg { 0: 0, enable: false, sre: false, fcl: false, ps: 0, is: 0, tia: 0, tib: 0, tic: 0, tid: 0 }, psr: RegisterPSR { 0: 0, bus_error: false, limit_violation: false, supervisor_violation: false, access_level_violatiom: false, write_protected: false, invalid: false, modified: false, gate: false, globally_shared: false, level_number: 0 }, last_desc: 0 } }, running: true, breakpoints: [], cycles: 56026204, fdd: [FddStatus { present: true, ejected: false, motor: true, writing: false, track: 0, image_title: "Dark Castle", dirty: false }, FddStatus { present: true, ejected: true, motor: false, writing: false, track: 4, image_title: "", dirty: false }, FddStatus { present: false, ejected: true, motor: false, writing: false, track: 4, image_title: "", dirty: false }], model: Plus, speed: Uncapped, scsi: [None, None, None, None, None, None, None] } [2025-09-21T08:11:18Z INFO single] Event: NextCode [2025-09-21T08:11:18Z INFO single] Event: Status: EmulatorStatus { regs: RegisterFile { d: [1336, 3, 123, 0, 65535, 255, 74, 0], a: [4295647, 6098, 4295646, 4296238, 14678527, 15728638, 10485758], usp: 0, isp: 2095866, sr: RegisterSR { 0: 8960, sr: 8960, ccr: 0, c: false, v: false, z: false, n: false, x: false, int_prio_mask: 3, m: false, supervisor: true, trace: false }, pc: 4295772, dfc: 0, sfc: 0, vbr: 0, caar: 0, cacr: RegisterCACR { 0: 0, e: false, f: false, ce: false, c: false }, msp: 0, fpu: FpuRegisterFile { fp: [Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }], fpcr: RegisterFPCR { 0: 0, mode: 0, rnd: 0, prec: 0, exc: FpuExceptions { 0: 0, inex1: false, inex2: false, dz: false, unfl: false, ovfl: false, operr: false, snan: false, bsun: false } }, fpsr: RegisterFPSR { 0: 0, fpcc: 0, fpcc_nan: false, fpcc_i: false, fpcc_z: false, fpcc_n: false, quotient: 0, quotient_s: false, exs: FpuExceptions { 0: 0, inex1: false, inex2: false, dz: false, unfl: false, ovfl: false, operr: false, snan: false, bsun: false }, aexc: FpuAccruedExceptions { 0: 0, inex: false, dz: false, unfl: false, ovfl: false, iop: false, snan: false, bsun: false } }, fpiar: 0 }, pmmu: PmmuRegisterFile { crp: RootPointerReg { 0: 0, lu: false, limit: 0, sg: false, dt: 0, table_addr: 0 }, srp: RootPointerReg { 0: 0, lu: false, limit: 0, sg: false, dt: 0, table_addr: 0 }, drp: RootPointerReg { 0: 0, lu: false, limit: 0, sg: false, dt: 0, table_addr: 0 }, pcsr: RegisterPCSR { 0: 0, ta: 0, flush: false, lw: false }, cal: AccessLevelReg { 0: 0, al: 0 }, val: AccessLevelReg { 0: 0, al: 0 }, scc: 0, ac: AccessControlReg { 0: 0, mc: false, alc: 0, mds: 0 }, tc: TcReg { 0: 0, enable: false, sre: false, fcl: false, ps: 0, is: 0, tia: 0, tib: 0, tic: 0, tid: 0 }, psr: RegisterPSR { 0: 0, bus_error: false, limit_violation: false, supervisor_violation: false, access_level_violatiom: false, write_protected: false, invalid: false, modified: false, gate: false, globally_shared: false, level_number: 0 }, last_desc: 0 } }, running: true, breakpoints: [], cycles: 61136896, fdd: [FddStatus { present: true, ejected: false, motor: true, writing: false, track: 0, image_title: "Dark Castle", dirty: false }, FddStatus { present: true, ejected: true, motor: false, writing: false, track: 4, image_title: "", dirty: false }, FddStatus { present: false, ejected: true, motor: false, writing: false, track: 4, image_title: "", dirty: false }], model: Plus, speed: Uncapped, scsi: [None, None, None, None, None, None, None] } [2025-09-21T08:11:18Z INFO single] Event: NextCode [2025-09-21T08:11:19Z INFO single] Event: Status: EmulatorStatus { regs: RegisterFile { d: [4294967232, 0, 0, 150, 4294836452, 0, 0, 0], a: [16496, 776, 4295899, 4296238, 14678527, 15728638, 10485758], usp: 0, isp: 2095866, sr: RegisterSR { 0: 8964, sr: 8964, ccr: 4, c: false, v: false, z: true, n: false, x: false, int_prio_mask: 3, m: false, supervisor: true, trace: false }, pc: 4296092, dfc: 0, sfc: 0, vbr: 0, caar: 0, cacr: RegisterCACR { 0: 0, e: false, f: false, ce: false, c: false }, msp: 0, fpu: FpuRegisterFile { fp: [Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }], fpcr: RegisterFPCR { 0: 0, mode: 0, rnd: 0, prec: 0, exc: FpuExceptions { 0: 0, inex1: false, inex2: false, dz: false, unfl: false, ovfl: false, operr: false, snan: false, bsun: false } }, fpsr: RegisterFPSR { 0: 0, fpcc: 0, fpcc_nan: false, fpcc_i: false, fpcc_z: false, fpcc_n: false, quotient: 0, quotient_s: false, exs: FpuExceptions { 0: 0, inex1: false, inex2: false, dz: false, unfl: false, ovfl: false, operr: false, snan: false, bsun: false }, aexc: FpuAccruedExceptions { 0: 0, inex: false, dz: false, unfl: false, ovfl: false, iop: false, snan: false, bsun: false } }, fpiar: 0 }, pmmu: PmmuRegisterFile { crp: RootPointerReg { 0: 0, lu: false, limit: 0, sg: false, dt: 0, table_addr: 0 }, srp: RootPointerReg { 0: 0, lu: false, limit: 0, sg: false, dt: 0, table_addr: 0 }, drp: RootPointerReg { 0: 0, lu: false, limit: 0, sg: false, dt: 0, table_addr: 0 }, pcsr: RegisterPCSR { 0: 0, ta: 0, flush: false, lw: false }, cal: AccessLevelReg { 0: 0, al: 0 }, val: AccessLevelReg { 0: 0, al: 0 }, scc: 0, ac: AccessControlReg { 0: 0, mc: false, alc: 0, mds: 0 }, tc: TcReg { 0: 0, enable: false, sre: false, fcl: false, ps: 0, is: 0, tia: 0, tib: 0, tic: 0, tid: 0 }, psr: RegisterPSR { 0: 0, bus_error: false, limit_violation: false, supervisor_violation: false, access_level_violatiom: false, write_protected: false, invalid: false, modified: false, gate: false, globally_shared: false, level_number: 0 }, last_desc: 0 } }, running: true, breakpoints: [], cycles: 66283352, fdd: [FddStatus { present: true, ejected: false, motor: true, writing: false, track: 0, image_title: "Dark Castle", dirty: false }, FddStatus { present: true, ejected: true, motor: false, writing: false, track: 4, image_title: "", dirty: false }, FddStatus { present: false, ejected: true, motor: false, writing: false, track: 4, image_title: "", dirty: false }], model: Plus, speed: Uncapped, scsi: [None, None, None, None, None, None, None] } [2025-09-21T08:11:19Z INFO single] Event: NextCode [2025-09-21T08:11:19Z INFO single] Event: Status: EmulatorStatus { regs: RegisterFile { d: [4294967232, 64, 0, 0, 4294836404, 123, 98, 129], a: [25061, 776, 4295899, 4296238, 14678527, 15728638, 10485758], usp: 0, isp: 2095824, sr: RegisterSR { 0: 8964, sr: 8964, ccr: 4, c: false, v: false, z: true, n: false, x: false, int_prio_mask: 3, m: false, supervisor: true, trace: false }, pc: 4296150, dfc: 0, sfc: 0, vbr: 0, caar: 0, cacr: RegisterCACR { 0: 0, e: false, f: false, ce: false, c: false }, msp: 0, fpu: FpuRegisterFile { fp: [Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }], fpcr: RegisterFPCR { 0: 0, mode: 0, rnd: 0, prec: 0, exc: FpuExceptions { 0: 0, inex1: false, inex2: false, dz: false, unfl: false, ovfl: false, operr: false, snan: false, bsun: false } }, fpsr: RegisterFPSR { 0: 0, fpcc: 0, fpcc_nan: false, fpcc_i: false, fpcc_z: false, fpcc_n: false, quotient: 0, quotient_s: false, exs: FpuExceptions { 0: 0, inex1: false, inex2: false, dz: false, unfl: false, ovfl: false, operr: false, snan: false, bsun: false }, aexc: FpuAccruedExceptions { 0: 0, inex: false, dz: false, unfl: false, ovfl: false, iop: false, snan: false, bsun: false } }, fpiar: 0 }, pmmu: PmmuRegisterFile { crp: RootPointerReg { 0: 0, lu: false, limit: 0, sg: false, dt: 0, table_addr: 0 }, srp: RootPointerReg { 0: 0, lu: false, limit: 0, sg: false, dt: 0, table_addr: 0 }, drp: RootPointerReg { 0: 0, lu: false, limit: 0, sg: false, dt: 0, table_addr: 0 }, pcsr: RegisterPCSR { 0: 0, ta: 0, flush: false, lw: false }, cal: AccessLevelReg { 0: 0, al: 0 }, val: AccessLevelReg { 0: 0, al: 0 }, scc: 0, ac: AccessControlReg { 0: 0, mc: false, alc: 0, mds: 0 }, tc: TcReg { 0: 0, enable: false, sre: false, fcl: false, ps: 0, is: 0, tia: 0, tib: 0, tic: 0, tid: 0 }, psr: RegisterPSR { 0: 0, bus_error: false, limit_violation: false, supervisor_violation: false, access_level_violatiom: false, write_protected: false, invalid: false, modified: false, gate: false, globally_shared: false, level_number: 0 }, last_desc: 0 } }, running: true, breakpoints: [], cycles: 71234806, fdd: [FddStatus { present: true, ejected: false, motor: true, writing: false, track: 77, image_title: "Dark Castle", dirty: false }, FddStatus { present: true, ejected: true, motor: false, writing: false, track: 4, image_title: "", dirty: false }, FddStatus { present: false, ejected: true, motor: false, writing: false, track: 4, image_title: "", dirty: false }], model: Plus, speed: Uncapped, scsi: [None, None, None, None, None, None, None] } [2025-09-21T08:11:19Z INFO single] Event: NextCode [2025-09-21T08:11:20Z INFO single] Event: Status: EmulatorStatus { regs: RegisterFile { d: [4294967232, 8, 0, 219, 4294836569, 118, 79, 235], a: [27536, 776, 4295899, 4296238, 14678527, 15728638, 10485758], usp: 0, isp: 2095718, sr: RegisterSR { 0: 8968, sr: 8968, ccr: 8, c: false, v: false, z: false, n: true, x: false, int_prio_mask: 3, m: false, supervisor: true, trace: false }, pc: 4296096, dfc: 0, sfc: 0, vbr: 0, caar: 0, cacr: RegisterCACR { 0: 0, e: false, f: false, ce: false, c: false }, msp: 0, fpu: FpuRegisterFile { fp: [Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }], fpcr: RegisterFPCR { 0: 0, mode: 0, rnd: 0, prec: 0, exc: FpuExceptions { 0: 0, inex1: false, inex2: false, dz: false, unfl: false, ovfl: false, operr: false, snan: false, bsun: false } }, fpsr: RegisterFPSR { 0: 0, fpcc: 0, fpcc_nan: false, fpcc_i: false, fpcc_z: false, fpcc_n: false, quotient: 0, quotient_s: false, exs: FpuExceptions { 0: 0, inex1: false, inex2: false, dz: false, unfl: false, ovfl: false, operr: false, snan: false, bsun: false }, aexc: FpuAccruedExceptions { 0: 0, inex: false, dz: false, unfl: false, ovfl: false, iop: false, snan: false, bsun: false } }, fpiar: 0 }, pmmu: PmmuRegisterFile { crp: RootPointerReg { 0: 0, lu: false, limit: 0, sg: false, dt: 0, table_addr: 0 }, srp: RootPointerReg { 0: 0, lu: false, limit: 0, sg: false, dt: 0, table_addr: 0 }, drp: RootPointerReg { 0: 0, lu: false, limit: 0, sg: false, dt: 0, table_addr: 0 }, pcsr: RegisterPCSR { 0: 0, ta: 0, flush: false, lw: false }, cal: AccessLevelReg { 0: 0, al: 0 }, val: AccessLevelReg { 0: 0, al: 0 }, scc: 0, ac: AccessControlReg { 0: 0, mc: false, alc: 0, mds: 0 }, tc: TcReg { 0: 0, enable: false, sre: false, fcl: false, ps: 0, is: 0, tia: 0, tib: 0, tic: 0, tid: 0 }, psr: RegisterPSR { 0: 0, bus_error: false, limit_violation: false, supervisor_violation: false, access_level_violatiom: false, write_protected: false, invalid: false, modified: false, gate: false, globally_shared: false, level_number: 0 }, last_desc: 0 } }, running: true, breakpoints: [], cycles: 75700178, fdd: [FddStatus { present: true, ejected: false, motor: true, writing: false, track: 74, image_title: "Dark Castle", dirty: false }, FddStatus { present: true, ejected: true, motor: false, writing: false, track: 4, image_title: "", dirty: false }, FddStatus { present: false, ejected: true, motor: false, writing: false, track: 4, image_title: "", dirty: false }], model: Plus, speed: Uncapped, scsi: [None, None, None, None, None, None, None] } [2025-09-21T08:11:20Z INFO single] Event: NextCode [2025-09-21T08:11:20Z INFO single] Event: Status: EmulatorStatus { regs: RegisterFile { d: [1, 74, 2, 1229867272, 255, 2560, 5, 11], a: [932, 2147489698, 4203454, 13994, 14006, 0, 13202], usp: 0, isp: 2095848, sr: RegisterSR { 0: 8192, sr: 8192, ccr: 0, c: false, v: false, z: false, n: false, x: false, int_prio_mask: 0, m: false, supervisor: true, trace: false }, pc: 4203556, dfc: 0, sfc: 0, vbr: 0, caar: 0, cacr: RegisterCACR { 0: 0, e: false, f: false, ce: false, c: false }, msp: 0, fpu: FpuRegisterFile { fp: [Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }], fpcr: RegisterFPCR { 0: 0, mode: 0, rnd: 0, prec: 0, exc: FpuExceptions { 0: 0, inex1: false, inex2: false, dz: false, unfl: false, ovfl: false, operr: false, snan: false, bsun: false } }, fpsr: RegisterFPSR { 0: 0, fpcc: 0, fpcc_nan: false, fpcc_i: false, fpcc_z: false, fpcc_n: false, quotient: 0, quotient_s: false, exs: FpuExceptions { 0: 0, inex1: false, inex2: false, dz: false, unfl: false, ovfl: false, operr: false, snan: false, bsun: false }, aexc: FpuAccruedExceptions { 0: 0, inex: false, dz: false, unfl: false, ovfl: false, iop: false, snan: false, bsun: false } }, fpiar: 0 }, pmmu: PmmuRegisterFile { crp: RootPointerReg { 0: 0, lu: false, limit: 0, sg: false, dt: 0, table_addr: 0 }, srp: RootPointerReg { 0: 0, lu: false, limit: 0, sg: false, dt: 0, table_addr: 0 }, drp: RootPointerReg { 0: 0, lu: false, limit: 0, sg: false, dt: 0, table_addr: 0 }, pcsr: RegisterPCSR { 0: 0, ta: 0, flush: false, lw: false }, cal: AccessLevelReg { 0: 0, al: 0 }, val: AccessLevelReg { 0: 0, al: 0 }, scc: 0, ac: AccessControlReg { 0: 0, mc: false, alc: 0, mds: 0 }, tc: TcReg { 0: 0, enable: false, sre: false, fcl: false, ps: 0, is: 0, tia: 0, tib: 0, tic: 0, tid: 0 }, psr: RegisterPSR { 0: 0, bus_error: false, limit_violation: false, supervisor_violation: false, access_level_violatiom: false, write_protected: false, invalid: false, modified: false, gate: false, globally_shared: false, level_number: 0 }, last_desc: 0 } }, running: true, breakpoints: [], cycles: 80523580, fdd: [FddStatus { present: true, ejected: false, motor: true, writing: false, track: 69, image_title: "Dark Castle", dirty: false }, FddStatus { present: true, ejected: true, motor: false, writing: false, track: 4, image_title: "", dirty: false }, FddStatus { present: false, ejected: true, motor: false, writing: false, track: 4, image_title: "", dirty: false }], model: Plus, speed: Uncapped, scsi: [None, None, None, None, None, None, None] } [2025-09-21T08:11:20Z INFO single] Event: NextCode [2025-09-21T08:11:21Z INFO single] Event: Status: EmulatorStatus { regs: RegisterFile { d: [1, 74, 10, 44, 217088, 3072, 217088, 217272], a: [932, 2147489698, 4203454, 54618, 52280, 55116, 13266], usp: 0, isp: 4171264, sr: RegisterSR { 0: 8192, sr: 8192, ccr: 0, c: false, v: false, z: false, n: false, x: false, int_prio_mask: 0, m: false, supervisor: true, trace: false }, pc: 4203556, dfc: 0, sfc: 0, vbr: 0, caar: 0, cacr: RegisterCACR { 0: 0, e: false, f: false, ce: false, c: false }, msp: 0, fpu: FpuRegisterFile { fp: [Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }], fpcr: RegisterFPCR { 0: 0, mode: 0, rnd: 0, prec: 0, exc: FpuExceptions { 0: 0, inex1: false, inex2: false, dz: false, unfl: false, ovfl: false, operr: false, snan: false, bsun: false } }, fpsr: RegisterFPSR { 0: 0, fpcc: 0, fpcc_nan: false, fpcc_i: false, fpcc_z: false, fpcc_n: false, quotient: 0, quotient_s: false, exs: FpuExceptions { 0: 0, inex1: false, inex2: false, dz: false, unfl: false, ovfl: false, operr: false, snan: false, bsun: false }, aexc: FpuAccruedExceptions { 0: 0, inex: false, dz: false, unfl: false, ovfl: false, iop: false, snan: false, bsun: false } }, fpiar: 0 }, pmmu: PmmuRegisterFile { crp: RootPointerReg { 0: 0, lu: false, limit: 0, sg: false, dt: 0, table_addr: 0 }, srp: RootPointerReg { 0: 0, lu: false, limit: 0, sg: false, dt: 0, table_addr: 0 }, drp: RootPointerReg { 0: 0, lu: false, limit: 0, sg: false, dt: 0, table_addr: 0 }, pcsr: RegisterPCSR { 0: 0, ta: 0, flush: false, lw: false }, cal: AccessLevelReg { 0: 0, al: 0 }, val: AccessLevelReg { 0: 0, al: 0 }, scc: 0, ac: AccessControlReg { 0: 0, mc: false, alc: 0, mds: 0 }, tc: TcReg { 0: 0, enable: false, sre: false, fcl: false, ps: 0, is: 0, tia: 0, tib: 0, tic: 0, tid: 0 }, psr: RegisterPSR { 0: 0, bus_error: false, limit_violation: false, supervisor_violation: false, access_level_violatiom: false, write_protected: false, invalid: false, modified: false, gate: false, globally_shared: false, level_number: 0 }, last_desc: 0 } }, running: true, breakpoints: [], cycles: 85649310, fdd: [FddStatus { present: true, ejected: false, motor: true, writing: false, track: 3, image_title: "Dark Castle", dirty: false }, FddStatus { present: true, ejected: true, motor: false, writing: false, track: 4, image_title: "", dirty: false }, FddStatus { present: false, ejected: true, motor: false, writing: false, track: 4, image_title: "", dirty: false }], model: Plus, speed: Uncapped, scsi: [None, None, None, None, None, None, None] } [2025-09-21T08:11:21Z INFO single] Event: NextCode [2025-09-21T08:11:21Z INFO single] Event: Status: EmulatorStatus { regs: RegisterFile { d: [4294967232, 65, 0, 234, 4294836602, 109, 29, 100], a: [80338, 776, 4295899, 4296238, 14678527, 15728638, 10485758], usp: 0, isp: 4171138, sr: RegisterSR { 0: 8960, sr: 8960, ccr: 0, c: false, v: false, z: false, n: false, x: false, int_prio_mask: 3, m: false, supervisor: true, trace: false }, pc: 4296138, dfc: 0, sfc: 0, vbr: 0, caar: 0, cacr: RegisterCACR { 0: 0, e: false, f: false, ce: false, c: false }, msp: 0, fpu: FpuRegisterFile { fp: [Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }], fpcr: RegisterFPCR { 0: 0, mode: 0, rnd: 0, prec: 0, exc: FpuExceptions { 0: 0, inex1: false, inex2: false, dz: false, unfl: false, ovfl: false, operr: false, snan: false, bsun: false } }, fpsr: RegisterFPSR { 0: 0, fpcc: 0, fpcc_nan: false, fpcc_i: false, fpcc_z: false, fpcc_n: false, quotient: 0, quotient_s: false, exs: FpuExceptions { 0: 0, inex1: false, inex2: false, dz: false, unfl: false, ovfl: false, operr: false, snan: false, bsun: false }, aexc: FpuAccruedExceptions { 0: 0, inex: false, dz: false, unfl: false, ovfl: false, iop: false, snan: false, bsun: false } }, fpiar: 0 }, pmmu: PmmuRegisterFile { crp: RootPointerReg { 0: 0, lu: false, limit: 0, sg: false, dt: 0, table_addr: 0 }, srp: RootPointerReg { 0: 0, lu: false, limit: 0, sg: false, dt: 0, table_addr: 0 }, drp: RootPointerReg { 0: 0, lu: false, limit: 0, sg: false, dt: 0, table_addr: 0 }, pcsr: RegisterPCSR { 0: 0, ta: 0, flush: false, lw: false }, cal: AccessLevelReg { 0: 0, al: 0 }, val: AccessLevelReg { 0: 0, al: 0 }, scc: 0, ac: AccessControlReg { 0: 0, mc: false, alc: 0, mds: 0 }, tc: TcReg { 0: 0, enable: false, sre: false, fcl: false, ps: 0, is: 0, tia: 0, tib: 0, tic: 0, tid: 0 }, psr: RegisterPSR { 0: 0, bus_error: false, limit_violation: false, supervisor_violation: false, access_level_violatiom: false, write_protected: false, invalid: false, modified: false, gate: false, globally_shared: false, level_number: 0 }, last_desc: 0 } }, running: true, breakpoints: [], cycles: 90858972, fdd: [FddStatus { present: true, ejected: false, motor: true, writing: false, track: 7, image_title: "Dark Castle", dirty: false }, FddStatus { present: true, ejected: true, motor: false, writing: false, track: 4, image_title: "", dirty: false }, FddStatus { present: false, ejected: true, motor: false, writing: false, track: 4, image_title: "", dirty: false }], model: Plus, speed: Uncapped, scsi: [None, None, None, None, None, None, None] } [2025-09-21T08:11:21Z INFO single] Event: NextCode [2025-09-21T08:11:22Z INFO single] Event: Status: EmulatorStatus { regs: RegisterFile { d: [4294967232, 1, 223, 221, 4294836521, 43, 231, 193], a: [100385, 776, 4295899, 4296238, 14678527, 15728638, 10485758], usp: 0, isp: 4171138, sr: RegisterSR { 0: 8968, sr: 8968, ccr: 8, c: false, v: false, z: false, n: true, x: false, int_prio_mask: 3, m: false, supervisor: true, trace: false }, pc: 4296080, dfc: 0, sfc: 0, vbr: 0, caar: 0, cacr: RegisterCACR { 0: 0, e: false, f: false, ce: false, c: false }, msp: 0, fpu: FpuRegisterFile { fp: [Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }], fpcr: RegisterFPCR { 0: 0, mode: 0, rnd: 0, prec: 0, exc: FpuExceptions { 0: 0, inex1: false, inex2: false, dz: false, unfl: false, ovfl: false, operr: false, snan: false, bsun: false } }, fpsr: RegisterFPSR { 0: 0, fpcc: 0, fpcc_nan: false, fpcc_i: false, fpcc_z: false, fpcc_n: false, quotient: 0, quotient_s: false, exs: FpuExceptions { 0: 0, inex1: false, inex2: false, dz: false, unfl: false, ovfl: false, operr: false, snan: false, bsun: false }, aexc: FpuAccruedExceptions { 0: 0, inex: false, dz: false, unfl: false, ovfl: false, iop: false, snan: false, bsun: false } }, fpiar: 0 }, pmmu: PmmuRegisterFile { crp: RootPointerReg { 0: 0, lu: false, limit: 0, sg: false, dt: 0, table_addr: 0 }, srp: RootPointerReg { 0: 0, lu: false, limit: 0, sg: false, dt: 0, table_addr: 0 }, drp: RootPointerReg { 0: 0, lu: false, limit: 0, sg: false, dt: 0, table_addr: 0 }, pcsr: RegisterPCSR { 0: 0, ta: 0, flush: false, lw: false }, cal: AccessLevelReg { 0: 0, al: 0 }, val: AccessLevelReg { 0: 0, al: 0 }, scc: 0, ac: AccessControlReg { 0: 0, mc: false, alc: 0, mds: 0 }, tc: TcReg { 0: 0, enable: false, sre: false, fcl: false, ps: 0, is: 0, tia: 0, tib: 0, tic: 0, tid: 0 }, psr: RegisterPSR { 0: 0, bus_error: false, limit_violation: false, supervisor_violation: false, access_level_violatiom: false, write_protected: false, invalid: false, modified: false, gate: false, globally_shared: false, level_number: 0 }, last_desc: 0 } }, running: true, breakpoints: [], cycles: 96078238, fdd: [FddStatus { present: true, ejected: false, motor: true, writing: false, track: 11, image_title: "Dark Castle", dirty: false }, FddStatus { present: true, ejected: true, motor: false, writing: false, track: 4, image_title: "", dirty: false }, FddStatus { present: false, ejected: true, motor: false, writing: false, track: 4, image_title: "", dirty: false }], model: Plus, speed: Uncapped, scsi: [None, None, None, None, None, None, None] } [2025-09-21T08:11:22Z INFO single] Event: NextCode [2025-09-21T08:11:22Z INFO single] Event: Status: EmulatorStatus { regs: RegisterFile { d: [4294967232, 0, 0, 210, 4294836704, 213, 71, 211], a: [123755, 776, 4295899, 4296238, 14678527, 15728638, 10485758], usp: 0, isp: 4171138, sr: RegisterSR { 0: 8980, sr: 8980, ccr: 20, c: false, v: false, z: true, n: false, x: true, int_prio_mask: 3, m: false, supervisor: true, trace: false }, pc: 4296118, dfc: 0, sfc: 0, vbr: 0, caar: 0, cacr: RegisterCACR { 0: 0, e: false, f: false, ce: false, c: false }, msp: 0, fpu: FpuRegisterFile { fp: [Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }], fpcr: RegisterFPCR { 0: 0, mode: 0, rnd: 0, prec: 0, exc: FpuExceptions { 0: 0, inex1: false, inex2: false, dz: false, unfl: false, ovfl: false, operr: false, snan: false, bsun: false } }, fpsr: RegisterFPSR { 0: 0, fpcc: 0, fpcc_nan: false, fpcc_i: false, fpcc_z: false, fpcc_n: false, quotient: 0, quotient_s: false, exs: FpuExceptions { 0: 0, inex1: false, inex2: false, dz: false, unfl: false, ovfl: false, operr: false, snan: false, bsun: false }, aexc: FpuAccruedExceptions { 0: 0, inex: false, dz: false, unfl: false, ovfl: false, iop: false, snan: false, bsun: false } }, fpiar: 0 }, pmmu: PmmuRegisterFile { crp: RootPointerReg { 0: 0, lu: false, limit: 0, sg: false, dt: 0, table_addr: 0 }, srp: RootPointerReg { 0: 0, lu: false, limit: 0, sg: false, dt: 0, table_addr: 0 }, drp: RootPointerReg { 0: 0, lu: false, limit: 0, sg: false, dt: 0, table_addr: 0 }, pcsr: RegisterPCSR { 0: 0, ta: 0, flush: false, lw: false }, cal: AccessLevelReg { 0: 0, al: 0 }, val: AccessLevelReg { 0: 0, al: 0 }, scc: 0, ac: AccessControlReg { 0: 0, mc: false, alc: 0, mds: 0 }, tc: TcReg { 0: 0, enable: false, sre: false, fcl: false, ps: 0, is: 0, tia: 0, tib: 0, tic: 0, tid: 0 }, psr: RegisterPSR { 0: 0, bus_error: false, limit_violation: false, supervisor_violation: false, access_level_violatiom: false, write_protected: false, invalid: false, modified: false, gate: false, globally_shared: false, level_number: 0 }, last_desc: 0 } }, running: true, breakpoints: [], cycles: 101122024, fdd: [FddStatus { present: true, ejected: false, motor: true, writing: false, track: 14, image_title: "Dark Castle", dirty: false }, FddStatus { present: true, ejected: true, motor: false, writing: false, track: 4, image_title: "", dirty: false }, FddStatus { present: false, ejected: true, motor: false, writing: false, track: 4, image_title: "", dirty: false }], model: Plus, speed: Uncapped, scsi: [None, None, None, None, None, None, None] } [2025-09-21T08:11:22Z INFO single] Event: NextCode [2025-09-21T08:11:23Z INFO single] Event: Status: EmulatorStatus { regs: RegisterFile { d: [4294967232, 240, 139, 166, 4294836476, 76, 52, 78], a: [139344, 776, 4295899, 4296238, 14678527, 15728638, 10485758], usp: 0, isp: 4171138, sr: RegisterSR { 0: 8968, sr: 8968, ccr: 8, c: false, v: false, z: false, n: true, x: false, int_prio_mask: 3, m: false, supervisor: true, trace: false }, pc: 4296132, dfc: 0, sfc: 0, vbr: 0, caar: 0, cacr: RegisterCACR { 0: 0, e: false, f: false, ce: false, c: false }, msp: 0, fpu: FpuRegisterFile { fp: [Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }], fpcr: RegisterFPCR { 0: 0, mode: 0, rnd: 0, prec: 0, exc: FpuExceptions { 0: 0, inex1: false, inex2: false, dz: false, unfl: false, ovfl: false, operr: false, snan: false, bsun: false } }, fpsr: RegisterFPSR { 0: 0, fpcc: 0, fpcc_nan: false, fpcc_i: false, fpcc_z: false, fpcc_n: false, quotient: 0, quotient_s: false, exs: FpuExceptions { 0: 0, inex1: false, inex2: false, dz: false, unfl: false, ovfl: false, operr: false, snan: false, bsun: false }, aexc: FpuAccruedExceptions { 0: 0, inex: false, dz: false, unfl: false, ovfl: false, iop: false, snan: false, bsun: false } }, fpiar: 0 }, pmmu: PmmuRegisterFile { crp: RootPointerReg { 0: 0, lu: false, limit: 0, sg: false, dt: 0, table_addr: 0 }, srp: RootPointerReg { 0: 0, lu: false, limit: 0, sg: false, dt: 0, table_addr: 0 }, drp: RootPointerReg { 0: 0, lu: false, limit: 0, sg: false, dt: 0, table_addr: 0 }, pcsr: RegisterPCSR { 0: 0, ta: 0, flush: false, lw: false }, cal: AccessLevelReg { 0: 0, al: 0 }, val: AccessLevelReg { 0: 0, al: 0 }, scc: 0, ac: AccessControlReg { 0: 0, mc: false, alc: 0, mds: 0 }, tc: TcReg { 0: 0, enable: false, sre: false, fcl: false, ps: 0, is: 0, tia: 0, tib: 0, tic: 0, tid: 0 }, psr: RegisterPSR { 0: 0, bus_error: false, limit_violation: false, supervisor_violation: false, access_level_violatiom: false, write_protected: false, invalid: false, modified: false, gate: false, globally_shared: false, level_number: 0 }, last_desc: 0 } }, running: true, breakpoints: [], cycles: 106265234, fdd: [FddStatus { present: true, ejected: false, motor: true, writing: false, track: 17, image_title: "Dark Castle", dirty: false }, FddStatus { present: true, ejected: true, motor: false, writing: false, track: 4, image_title: "", dirty: false }, FddStatus { present: false, ejected: true, motor: false, writing: false, track: 4, image_title: "", dirty: false }], model: Plus, speed: Uncapped, scsi: [None, None, None, None, None, None, None] } [2025-09-21T08:11:23Z INFO single] Event: NextCode [2025-09-21T08:11:23Z INFO single] Event: Status: EmulatorStatus { regs: RegisterFile { d: [4294967232, 255, 250, 178, 4294836644, 20, 202, 158], a: [163238, 776, 4295899, 4296238, 14678527, 15728638, 10485758], usp: 0, isp: 4171138, sr: RegisterSR { 0: 8968, sr: 8968, ccr: 8, c: false, v: false, z: false, n: true, x: false, int_prio_mask: 3, m: false, supervisor: true, trace: false }, pc: 4296084, dfc: 0, sfc: 0, vbr: 0, caar: 0, cacr: RegisterCACR { 0: 0, e: false, f: false, ce: false, c: false }, msp: 0, fpu: FpuRegisterFile { fp: [Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }], fpcr: RegisterFPCR { 0: 0, mode: 0, rnd: 0, prec: 0, exc: FpuExceptions { 0: 0, inex1: false, inex2: false, dz: false, unfl: false, ovfl: false, operr: false, snan: false, bsun: false } }, fpsr: RegisterFPSR { 0: 0, fpcc: 0, fpcc_nan: false, fpcc_i: false, fpcc_z: false, fpcc_n: false, quotient: 0, quotient_s: false, exs: FpuExceptions { 0: 0, inex1: false, inex2: false, dz: false, unfl: false, ovfl: false, operr: false, snan: false, bsun: false }, aexc: FpuAccruedExceptions { 0: 0, inex: false, dz: false, unfl: false, ovfl: false, iop: false, snan: false, bsun: false } }, fpiar: 0 }, pmmu: PmmuRegisterFile { crp: RootPointerReg { 0: 0, lu: false, limit: 0, sg: false, dt: 0, table_addr: 0 }, srp: RootPointerReg { 0: 0, lu: false, limit: 0, sg: false, dt: 0, table_addr: 0 }, drp: RootPointerReg { 0: 0, lu: false, limit: 0, sg: false, dt: 0, table_addr: 0 }, pcsr: RegisterPCSR { 0: 0, ta: 0, flush: false, lw: false }, cal: AccessLevelReg { 0: 0, al: 0 }, val: AccessLevelReg { 0: 0, al: 0 }, scc: 0, ac: AccessControlReg { 0: 0, mc: false, alc: 0, mds: 0 }, tc: TcReg { 0: 0, enable: false, sre: false, fcl: false, ps: 0, is: 0, tia: 0, tib: 0, tic: 0, tid: 0 }, psr: RegisterPSR { 0: 0, bus_error: false, limit_violation: false, supervisor_violation: false, access_level_violatiom: false, write_protected: false, invalid: false, modified: false, gate: false, globally_shared: false, level_number: 0 }, last_desc: 0 } }, running: true, breakpoints: [], cycles: 111313504, fdd: [FddStatus { present: true, ejected: false, motor: true, writing: false, track: 21, image_title: "Dark Castle", dirty: false }, FddStatus { present: true, ejected: true, motor: false, writing: false, track: 4, image_title: "", dirty: false }, FddStatus { present: false, ejected: true, motor: false, writing: false, track: 4, image_title: "", dirty: false }], model: Plus, speed: Uncapped, scsi: [None, None, None, None, None, None, None] } [2025-09-21T08:11:23Z INFO single] Event: NextCode [2025-09-21T08:11:24Z INFO single] Event: Status: EmulatorStatus { regs: RegisterFile { d: [1, 74, 10, 44, 217088, 3072, 217088, 217272], a: [932, 2147489698, 4203454, 54618, 52280, 55116, 13266], usp: 0, isp: 4171264, sr: RegisterSR { 0: 8192, sr: 8192, ccr: 0, c: false, v: false, z: false, n: false, x: false, int_prio_mask: 0, m: false, supervisor: true, trace: false }, pc: 4203552, dfc: 0, sfc: 0, vbr: 0, caar: 0, cacr: RegisterCACR { 0: 0, e: false, f: false, ce: false, c: false }, msp: 0, fpu: FpuRegisterFile { fp: [Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }], fpcr: RegisterFPCR { 0: 0, mode: 0, rnd: 0, prec: 0, exc: FpuExceptions { 0: 0, inex1: false, inex2: false, dz: false, unfl: false, ovfl: false, operr: false, snan: false, bsun: false } }, fpsr: RegisterFPSR { 0: 0, fpcc: 0, fpcc_nan: false, fpcc_i: false, fpcc_z: false, fpcc_n: false, quotient: 0, quotient_s: false, exs: FpuExceptions { 0: 0, inex1: false, inex2: false, dz: false, unfl: false, ovfl: false, operr: false, snan: false, bsun: false }, aexc: FpuAccruedExceptions { 0: 0, inex: false, dz: false, unfl: false, ovfl: false, iop: false, snan: false, bsun: false } }, fpiar: 0 }, pmmu: PmmuRegisterFile { crp: RootPointerReg { 0: 0, lu: false, limit: 0, sg: false, dt: 0, table_addr: 0 }, srp: RootPointerReg { 0: 0, lu: false, limit: 0, sg: false, dt: 0, table_addr: 0 }, drp: RootPointerReg { 0: 0, lu: false, limit: 0, sg: false, dt: 0, table_addr: 0 }, pcsr: RegisterPCSR { 0: 0, ta: 0, flush: false, lw: false }, cal: AccessLevelReg { 0: 0, al: 0 }, val: AccessLevelReg { 0: 0, al: 0 }, scc: 0, ac: AccessControlReg { 0: 0, mc: false, alc: 0, mds: 0 }, tc: TcReg { 0: 0, enable: false, sre: false, fcl: false, ps: 0, is: 0, tia: 0, tib: 0, tic: 0, tid: 0 }, psr: RegisterPSR { 0: 0, bus_error: false, limit_violation: false, supervisor_violation: false, access_level_violatiom: false, write_protected: false, invalid: false, modified: false, gate: false, globally_shared: false, level_number: 0 }, last_desc: 0 } }, running: true, breakpoints: [], cycles: 118821734, fdd: [FddStatus { present: true, ejected: false, motor: true, writing: false, track: 0, image_title: "Dark Castle", dirty: false }, FddStatus { present: true, ejected: true, motor: false, writing: false, track: 4, image_title: "", dirty: false }, FddStatus { present: false, ejected: true, motor: false, writing: false, track: 4, image_title: "", dirty: false }], model: Plus, speed: Uncapped, scsi: [None, None, None, None, None, None, None] } [2025-09-21T08:11:24Z INFO single] Event: NextCode [2025-09-21T08:11:24Z INFO single] Event: Status: EmulatorStatus { regs: RegisterFile { d: [4294967232, 40, 0, 172, 33423367, 0, 0, 0], a: [71222, 767, 4295899, 4296238, 14678527, 15728638, 10485758], usp: 0, isp: 4171114, sr: RegisterSR { 0: 8960, sr: 8960, ccr: 0, c: false, v: false, z: false, n: false, x: false, int_prio_mask: 3, m: false, supervisor: true, trace: false }, pc: 4295992, dfc: 0, sfc: 0, vbr: 0, caar: 0, cacr: RegisterCACR { 0: 0, e: false, f: false, ce: false, c: false }, msp: 0, fpu: FpuRegisterFile { fp: [Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }], fpcr: RegisterFPCR { 0: 0, mode: 0, rnd: 0, prec: 0, exc: FpuExceptions { 0: 0, inex1: false, inex2: false, dz: false, unfl: false, ovfl: false, operr: false, snan: false, bsun: false } }, fpsr: RegisterFPSR { 0: 0, fpcc: 0, fpcc_nan: false, fpcc_i: false, fpcc_z: false, fpcc_n: false, quotient: 0, quotient_s: false, exs: FpuExceptions { 0: 0, inex1: false, inex2: false, dz: false, unfl: false, ovfl: false, operr: false, snan: false, bsun: false }, aexc: FpuAccruedExceptions { 0: 0, inex: false, dz: false, unfl: false, ovfl: false, iop: false, snan: false, bsun: false } }, fpiar: 0 }, pmmu: PmmuRegisterFile { crp: RootPointerReg { 0: 0, lu: false, limit: 0, sg: false, dt: 0, table_addr: 0 }, srp: RootPointerReg { 0: 0, lu: false, limit: 0, sg: false, dt: 0, table_addr: 0 }, drp: RootPointerReg { 0: 0, lu: false, limit: 0, sg: false, dt: 0, table_addr: 0 }, pcsr: RegisterPCSR { 0: 0, ta: 0, flush: false, lw: false }, cal: AccessLevelReg { 0: 0, al: 0 }, val: AccessLevelReg { 0: 0, al: 0 }, scc: 0, ac: AccessControlReg { 0: 0, mc: false, alc: 0, mds: 0 }, tc: TcReg { 0: 0, enable: false, sre: false, fcl: false, ps: 0, is: 0, tia: 0, tib: 0, tic: 0, tid: 0 }, psr: RegisterPSR { 0: 0, bus_error: false, limit_violation: false, supervisor_violation: false, access_level_violatiom: false, write_protected: false, invalid: false, modified: false, gate: false, globally_shared: false, level_number: 0 }, last_desc: 0 } }, running: true, breakpoints: [], cycles: 126849148, fdd: [FddStatus { present: true, ejected: false, motor: true, writing: false, track: 6, image_title: "Dark Castle", dirty: false }, FddStatus { present: true, ejected: true, motor: false, writing: false, track: 4, image_title: "", dirty: false }, FddStatus { present: false, ejected: true, motor: false, writing: false, track: 4, image_title: "", dirty: false }], model: Plus, speed: Uncapped, scsi: [None, None, None, None, None, None, None] } [2025-09-21T08:11:24Z INFO single] Event: NextCode [2025-09-21T08:11:25Z INFO single] Event: Status: EmulatorStatus { regs: RegisterFile { d: [4294967232, 176, 128, 179, 4294836611, 9, 29, 248], a: [106677, 776, 4295899, 4296238, 14678527, 15728638, 10485758], usp: 0, isp: 4171114, sr: RegisterSR { 0: 8968, sr: 8968, ccr: 8, c: false, v: false, z: false, n: true, x: false, int_prio_mask: 3, m: false, supervisor: true, trace: false }, pc: 4296096, dfc: 0, sfc: 0, vbr: 0, caar: 0, cacr: RegisterCACR { 0: 0, e: false, f: false, ce: false, c: false }, msp: 0, fpu: FpuRegisterFile { fp: [Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }], fpcr: RegisterFPCR { 0: 0, mode: 0, rnd: 0, prec: 0, exc: FpuExceptions { 0: 0, inex1: false, inex2: false, dz: false, unfl: false, ovfl: false, operr: false, snan: false, bsun: false } }, fpsr: RegisterFPSR { 0: 0, fpcc: 0, fpcc_nan: false, fpcc_i: false, fpcc_z: false, fpcc_n: false, quotient: 0, quotient_s: false, exs: FpuExceptions { 0: 0, inex1: false, inex2: false, dz: false, unfl: false, ovfl: false, operr: false, snan: false, bsun: false }, aexc: FpuAccruedExceptions { 0: 0, inex: false, dz: false, unfl: false, ovfl: false, iop: false, snan: false, bsun: false } }, fpiar: 0 }, pmmu: PmmuRegisterFile { crp: RootPointerReg { 0: 0, lu: false, limit: 0, sg: false, dt: 0, table_addr: 0 }, srp: RootPointerReg { 0: 0, lu: false, limit: 0, sg: false, dt: 0, table_addr: 0 }, drp: RootPointerReg { 0: 0, lu: false, limit: 0, sg: false, dt: 0, table_addr: 0 }, pcsr: RegisterPCSR { 0: 0, ta: 0, flush: false, lw: false }, cal: AccessLevelReg { 0: 0, al: 0 }, val: AccessLevelReg { 0: 0, al: 0 }, scc: 0, ac: AccessControlReg { 0: 0, mc: false, alc: 0, mds: 0 }, tc: TcReg { 0: 0, enable: false, sre: false, fcl: false, ps: 0, is: 0, tia: 0, tib: 0, tic: 0, tid: 0 }, psr: RegisterPSR { 0: 0, bus_error: false, limit_violation: false, supervisor_violation: false, access_level_violatiom: false, write_protected: false, invalid: false, modified: false, gate: false, globally_shared: false, level_number: 0 }, last_desc: 0 } }, running: true, breakpoints: [], cycles: 135669654, fdd: [FddStatus { present: true, ejected: false, motor: true, writing: false, track: 12, image_title: "Dark Castle", dirty: false }, FddStatus { present: true, ejected: true, motor: false, writing: false, track: 4, image_title: "", dirty: false }, FddStatus { present: false, ejected: true, motor: false, writing: false, track: 4, image_title: "", dirty: false }], model: Plus, speed: Uncapped, scsi: [None, None, None, None, None, None, None] } [2025-09-21T08:11:25Z INFO single] Event: NextCode [2025-09-21T08:11:25Z INFO single] Event: Status: EmulatorStatus { regs: RegisterFile { d: [4294967232, 241, 192, 0, 4294836224, 92, 215, 195], a: [31012, 776, 4295899, 4296238, 14678527, 15728638, 10485758], usp: 0, isp: 4171114, sr: RegisterSR { 0: 8964, sr: 8964, ccr: 4, c: false, v: false, z: true, n: false, x: false, int_prio_mask: 3, m: false, supervisor: true, trace: false }, pc: 4296308, dfc: 0, sfc: 0, vbr: 0, caar: 0, cacr: RegisterCACR { 0: 0, e: false, f: false, ce: false, c: false }, msp: 0, fpu: FpuRegisterFile { fp: [Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }], fpcr: RegisterFPCR { 0: 0, mode: 0, rnd: 0, prec: 0, exc: FpuExceptions { 0: 0, inex1: false, inex2: false, dz: false, unfl: false, ovfl: false, operr: false, snan: false, bsun: false } }, fpsr: RegisterFPSR { 0: 0, fpcc: 0, fpcc_nan: false, fpcc_i: false, fpcc_z: false, fpcc_n: false, quotient: 0, quotient_s: false, exs: FpuExceptions { 0: 0, inex1: false, inex2: false, dz: false, unfl: false, ovfl: false, operr: false, snan: false, bsun: false }, aexc: FpuAccruedExceptions { 0: 0, inex: false, dz: false, unfl: false, ovfl: false, iop: false, snan: false, bsun: false } }, fpiar: 0 }, pmmu: PmmuRegisterFile { crp: RootPointerReg { 0: 0, lu: false, limit: 0, sg: false, dt: 0, table_addr: 0 }, srp: RootPointerReg { 0: 0, lu: false, limit: 0, sg: false, dt: 0, table_addr: 0 }, drp: RootPointerReg { 0: 0, lu: false, limit: 0, sg: false, dt: 0, table_addr: 0 }, pcsr: RegisterPCSR { 0: 0, ta: 0, flush: false, lw: false }, cal: AccessLevelReg { 0: 0, al: 0 }, val: AccessLevelReg { 0: 0, al: 0 }, scc: 0, ac: AccessControlReg { 0: 0, mc: false, alc: 0, mds: 0 }, tc: TcReg { 0: 0, enable: false, sre: false, fcl: false, ps: 0, is: 0, tia: 0, tib: 0, tic: 0, tid: 0 }, psr: RegisterPSR { 0: 0, bus_error: false, limit_violation: false, supervisor_violation: false, access_level_violatiom: false, write_protected: false, invalid: false, modified: false, gate: false, globally_shared: false, level_number: 0 }, last_desc: 0 } }, running: true, breakpoints: [], cycles: 142832280, fdd: [FddStatus { present: true, ejected: false, motor: true, writing: false, track: 15, image_title: "Dark Castle", dirty: false }, FddStatus { present: true, ejected: true, motor: false, writing: false, track: 4, image_title: "", dirty: false }, FddStatus { present: false, ejected: true, motor: false, writing: false, track: 4, image_title: "", dirty: false }], model: Plus, speed: Uncapped, scsi: [None, None, None, None, None, None, None] } [2025-09-21T08:11:25Z INFO single] Event: NextCode [2025-09-21T08:11:26Z INFO single] Event: Status: EmulatorStatus { regs: RegisterFile { d: [1436, 3, 121, 0, 10, 244, 74, 17], a: [4295647, 6098, 4295646, 4296238, 14678527, 15728638, 10485758], usp: 0, isp: 4171184, sr: RegisterSR { 0: 8960, sr: 8960, ccr: 0, c: false, v: false, z: false, n: false, x: false, int_prio_mask: 3, m: false, supervisor: true, trace: false }, pc: 4295796, dfc: 0, sfc: 0, vbr: 0, caar: 0, cacr: RegisterCACR { 0: 0, e: false, f: false, ce: false, c: false }, msp: 0, fpu: FpuRegisterFile { fp: [Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }], fpcr: RegisterFPCR { 0: 0, mode: 0, rnd: 0, prec: 0, exc: FpuExceptions { 0: 0, inex1: false, inex2: false, dz: false, unfl: false, ovfl: false, operr: false, snan: false, bsun: false } }, fpsr: RegisterFPSR { 0: 0, fpcc: 0, fpcc_nan: false, fpcc_i: false, fpcc_z: false, fpcc_n: false, quotient: 0, quotient_s: false, exs: FpuExceptions { 0: 0, inex1: false, inex2: false, dz: false, unfl: false, ovfl: false, operr: false, snan: false, bsun: false }, aexc: FpuAccruedExceptions { 0: 0, inex: false, dz: false, unfl: false, ovfl: false, iop: false, snan: false, bsun: false } }, fpiar: 0 }, pmmu: PmmuRegisterFile { crp: RootPointerReg { 0: 0, lu: false, limit: 0, sg: false, dt: 0, table_addr: 0 }, srp: RootPointerReg { 0: 0, lu: false, limit: 0, sg: false, dt: 0, table_addr: 0 }, drp: RootPointerReg { 0: 0, lu: false, limit: 0, sg: false, dt: 0, table_addr: 0 }, pcsr: RegisterPCSR { 0: 0, ta: 0, flush: false, lw: false }, cal: AccessLevelReg { 0: 0, al: 0 }, val: AccessLevelReg { 0: 0, al: 0 }, scc: 0, ac: AccessControlReg { 0: 0, mc: false, alc: 0, mds: 0 }, tc: TcReg { 0: 0, enable: false, sre: false, fcl: false, ps: 0, is: 0, tia: 0, tib: 0, tic: 0, tid: 0 }, psr: RegisterPSR { 0: 0, bus_error: false, limit_violation: false, supervisor_violation: false, access_level_violatiom: false, write_protected: false, invalid: false, modified: false, gate: false, globally_shared: false, level_number: 0 }, last_desc: 0 } }, running: true, breakpoints: [], cycles: 147761816, fdd: [FddStatus { present: true, ejected: false, motor: true, writing: false, track: 17, image_title: "Dark Castle", dirty: false }, FddStatus { present: true, ejected: true, motor: false, writing: false, track: 4, image_title: "", dirty: false }, FddStatus { present: false, ejected: true, motor: false, writing: false, track: 4, image_title: "", dirty: false }], model: Plus, speed: Uncapped, scsi: [None, None, None, None, None, None, None] } [2025-09-21T08:11:26Z INFO single] Event: NextCode [2025-09-21T08:11:26Z INFO single] Event: Status: EmulatorStatus { regs: RegisterFile { d: [4294967232, 0, 242, 0, 4294836593, 79, 22, 176], a: [160351, 776, 4295899, 4296238, 14678527, 15728638, 10485758], usp: 0, isp: 4171114, sr: RegisterSR { 0: 8980, sr: 8980, ccr: 20, c: false, v: false, z: true, n: false, x: true, int_prio_mask: 3, m: false, supervisor: true, trace: false }, pc: 4296150, dfc: 0, sfc: 0, vbr: 0, caar: 0, cacr: RegisterCACR { 0: 0, e: false, f: false, ce: false, c: false }, msp: 0, fpu: FpuRegisterFile { fp: [Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }], fpcr: RegisterFPCR { 0: 0, mode: 0, rnd: 0, prec: 0, exc: FpuExceptions { 0: 0, inex1: false, inex2: false, dz: false, unfl: false, ovfl: false, operr: false, snan: false, bsun: false } }, fpsr: RegisterFPSR { 0: 0, fpcc: 0, fpcc_nan: false, fpcc_i: false, fpcc_z: false, fpcc_n: false, quotient: 0, quotient_s: false, exs: FpuExceptions { 0: 0, inex1: false, inex2: false, dz: false, unfl: false, ovfl: false, operr: false, snan: false, bsun: false }, aexc: FpuAccruedExceptions { 0: 0, inex: false, dz: false, unfl: false, ovfl: false, iop: false, snan: false, bsun: false } }, fpiar: 0 }, pmmu: PmmuRegisterFile { crp: RootPointerReg { 0: 0, lu: false, limit: 0, sg: false, dt: 0, table_addr: 0 }, srp: RootPointerReg { 0: 0, lu: false, limit: 0, sg: false, dt: 0, table_addr: 0 }, drp: RootPointerReg { 0: 0, lu: false, limit: 0, sg: false, dt: 0, table_addr: 0 }, pcsr: RegisterPCSR { 0: 0, ta: 0, flush: false, lw: false }, cal: AccessLevelReg { 0: 0, al: 0 }, val: AccessLevelReg { 0: 0, al: 0 }, scc: 0, ac: AccessControlReg { 0: 0, mc: false, alc: 0, mds: 0 }, tc: TcReg { 0: 0, enable: false, sre: false, fcl: false, ps: 0, is: 0, tia: 0, tib: 0, tic: 0, tid: 0 }, psr: RegisterPSR { 0: 0, bus_error: false, limit_violation: false, supervisor_violation: false, access_level_violatiom: false, write_protected: false, invalid: false, modified: false, gate: false, globally_shared: false, level_number: 0 }, last_desc: 0 } }, running: true, breakpoints: [], cycles: 156395644, fdd: [FddStatus { present: true, ejected: false, motor: true, writing: false, track: 21, image_title: "Dark Castle", dirty: false }, FddStatus { present: true, ejected: true, motor: false, writing: false, track: 4, image_title: "", dirty: false }, FddStatus { present: false, ejected: true, motor: false, writing: false, track: 4, image_title: "", dirty: false }], model: Plus, speed: Uncapped, scsi: [None, None, None, None, None, None, None] } [2025-09-21T08:11:26Z INFO single] Event: NextCode [2025-09-21T08:11:27Z INFO single] Event: Status: EmulatorStatus { regs: RegisterFile { d: [1, 74, 10, 264, 6144, 115712, 6144, 6213], a: [932, 2147489698, 4203454, 167620, 52280, 167892, 13266], usp: 0, isp: 4171240, sr: RegisterSR { 0: 8192, sr: 8192, ccr: 0, c: false, v: false, z: false, n: false, x: false, int_prio_mask: 0, m: false, supervisor: true, trace: false }, pc: 4203556, dfc: 0, sfc: 0, vbr: 0, caar: 0, cacr: RegisterCACR { 0: 0, e: false, f: false, ce: false, c: false }, msp: 0, fpu: FpuRegisterFile { fp: [Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }], fpcr: RegisterFPCR { 0: 0, mode: 0, rnd: 0, prec: 0, exc: FpuExceptions { 0: 0, inex1: false, inex2: false, dz: false, unfl: false, ovfl: false, operr: false, snan: false, bsun: false } }, fpsr: RegisterFPSR { 0: 0, fpcc: 0, fpcc_nan: false, fpcc_i: false, fpcc_z: false, fpcc_n: false, quotient: 0, quotient_s: false, exs: FpuExceptions { 0: 0, inex1: false, inex2: false, dz: false, unfl: false, ovfl: false, operr: false, snan: false, bsun: false }, aexc: FpuAccruedExceptions { 0: 0, inex: false, dz: false, unfl: false, ovfl: false, iop: false, snan: false, bsun: false } }, fpiar: 0 }, pmmu: PmmuRegisterFile { crp: RootPointerReg { 0: 0, lu: false, limit: 0, sg: false, dt: 0, table_addr: 0 }, srp: RootPointerReg { 0: 0, lu: false, limit: 0, sg: false, dt: 0, table_addr: 0 }, drp: RootPointerReg { 0: 0, lu: false, limit: 0, sg: false, dt: 0, table_addr: 0 }, pcsr: RegisterPCSR { 0: 0, ta: 0, flush: false, lw: false }, cal: AccessLevelReg { 0: 0, al: 0 }, val: AccessLevelReg { 0: 0, al: 0 }, scc: 0, ac: AccessControlReg { 0: 0, mc: false, alc: 0, mds: 0 }, tc: TcReg { 0: 0, enable: false, sre: false, fcl: false, ps: 0, is: 0, tia: 0, tib: 0, tic: 0, tid: 0 }, psr: RegisterPSR { 0: 0, bus_error: false, limit_violation: false, supervisor_violation: false, access_level_violatiom: false, write_protected: false, invalid: false, modified: false, gate: false, globally_shared: false, level_number: 0 }, last_desc: 0 } }, running: true, breakpoints: [], cycles: 164063660, fdd: [FddStatus { present: true, ejected: false, motor: true, writing: false, track: 0, image_title: "Dark Castle", dirty: false }, FddStatus { present: true, ejected: true, motor: false, writing: false, track: 4, image_title: "", dirty: false }, FddStatus { present: false, ejected: true, motor: false, writing: false, track: 4, image_title: "", dirty: false }], model: Plus, speed: Uncapped, scsi: [None, None, None, None, None, None, None] } [2025-09-21T08:11:27Z INFO single] Event: NextCode [2025-09-21T08:11:27Z INFO single] Event: Status: EmulatorStatus { regs: RegisterFile { d: [1, 74, 9, 1347437320, 345087, 121856, 238, 16], a: [932, 2147489698, 4203454, 13994, 14546, 0, 13202], usp: 0, isp: 4171236, sr: RegisterSR { 0: 8192, sr: 8192, ccr: 0, c: false, v: false, z: false, n: false, x: false, int_prio_mask: 0, m: false, supervisor: true, trace: false }, pc: 4203552, dfc: 0, sfc: 0, vbr: 0, caar: 0, cacr: RegisterCACR { 0: 0, e: false, f: false, ce: false, c: false }, msp: 0, fpu: FpuRegisterFile { fp: [Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }], fpcr: RegisterFPCR { 0: 0, mode: 0, rnd: 0, prec: 0, exc: FpuExceptions { 0: 0, inex1: false, inex2: false, dz: false, unfl: false, ovfl: false, operr: false, snan: false, bsun: false } }, fpsr: RegisterFPSR { 0: 0, fpcc: 0, fpcc_nan: false, fpcc_i: false, fpcc_z: false, fpcc_n: false, quotient: 0, quotient_s: false, exs: FpuExceptions { 0: 0, inex1: false, inex2: false, dz: false, unfl: false, ovfl: false, operr: false, snan: false, bsun: false }, aexc: FpuAccruedExceptions { 0: 0, inex: false, dz: false, unfl: false, ovfl: false, iop: false, snan: false, bsun: false } }, fpiar: 0 }, pmmu: PmmuRegisterFile { crp: RootPointerReg { 0: 0, lu: false, limit: 0, sg: false, dt: 0, table_addr: 0 }, srp: RootPointerReg { 0: 0, lu: false, limit: 0, sg: false, dt: 0, table_addr: 0 }, drp: RootPointerReg { 0: 0, lu: false, limit: 0, sg: false, dt: 0, table_addr: 0 }, pcsr: RegisterPCSR { 0: 0, ta: 0, flush: false, lw: false }, cal: AccessLevelReg { 0: 0, al: 0 }, val: AccessLevelReg { 0: 0, al: 0 }, scc: 0, ac: AccessControlReg { 0: 0, mc: false, alc: 0, mds: 0 }, tc: TcReg { 0: 0, enable: false, sre: false, fcl: false, ps: 0, is: 0, tia: 0, tib: 0, tic: 0, tid: 0 }, psr: RegisterPSR { 0: 0, bus_error: false, limit_violation: false, supervisor_violation: false, access_level_violatiom: false, write_protected: false, invalid: false, modified: false, gate: false, globally_shared: false, level_number: 0 }, last_desc: 0 } }, running: true, breakpoints: [], cycles: 172636310, fdd: [FddStatus { present: true, ejected: false, motor: true, writing: false, track: 23, image_title: "Dark Castle", dirty: false }, FddStatus { present: true, ejected: true, motor: false, writing: false, track: 4, image_title: "", dirty: false }, FddStatus { present: false, ejected: true, motor: false, writing: false, track: 4, image_title: "", dirty: false }], model: Plus, speed: Uncapped, scsi: [None, None, None, None, None, None, None] } [2025-09-21T08:11:27Z INFO single] Event: NextCode [2025-09-21T08:11:28Z INFO single] Event: Status: EmulatorStatus { regs: RegisterFile { d: [1, 74, 9, 1347437320, 345087, 121856, 238, 16], a: [932, 2147489698, 4203454, 13994, 14546, 0, 13202], usp: 0, isp: 4171236, sr: RegisterSR { 0: 8192, sr: 8192, ccr: 0, c: false, v: false, z: false, n: false, x: false, int_prio_mask: 0, m: false, supervisor: true, trace: false }, pc: 4203552, dfc: 0, sfc: 0, vbr: 0, caar: 0, cacr: RegisterCACR { 0: 0, e: false, f: false, ce: false, c: false }, msp: 0, fpu: FpuRegisterFile { fp: [Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }], fpcr: RegisterFPCR { 0: 0, mode: 0, rnd: 0, prec: 0, exc: FpuExceptions { 0: 0, inex1: false, inex2: false, dz: false, unfl: false, ovfl: false, operr: false, snan: false, bsun: false } }, fpsr: RegisterFPSR { 0: 0, fpcc: 0, fpcc_nan: false, fpcc_i: false, fpcc_z: false, fpcc_n: false, quotient: 0, quotient_s: false, exs: FpuExceptions { 0: 0, inex1: false, inex2: false, dz: false, unfl: false, ovfl: false, operr: false, snan: false, bsun: false }, aexc: FpuAccruedExceptions { 0: 0, inex: false, dz: false, unfl: false, ovfl: false, iop: false, snan: false, bsun: false } }, fpiar: 0 }, pmmu: PmmuRegisterFile { crp: RootPointerReg { 0: 0, lu: false, limit: 0, sg: false, dt: 0, table_addr: 0 }, srp: RootPointerReg { 0: 0, lu: false, limit: 0, sg: false, dt: 0, table_addr: 0 }, drp: RootPointerReg { 0: 0, lu: false, limit: 0, sg: false, dt: 0, table_addr: 0 }, pcsr: RegisterPCSR { 0: 0, ta: 0, flush: false, lw: false }, cal: AccessLevelReg { 0: 0, al: 0 }, val: AccessLevelReg { 0: 0, al: 0 }, scc: 0, ac: AccessControlReg { 0: 0, mc: false, alc: 0, mds: 0 }, tc: TcReg { 0: 0, enable: false, sre: false, fcl: false, ps: 0, is: 0, tia: 0, tib: 0, tic: 0, tid: 0 }, psr: RegisterPSR { 0: 0, bus_error: false, limit_violation: false, supervisor_violation: false, access_level_violatiom: false, write_protected: false, invalid: false, modified: false, gate: false, globally_shared: false, level_number: 0 }, last_desc: 0 } }, running: true, breakpoints: [], cycles: 180575878, fdd: [FddStatus { present: true, ejected: false, motor: true, writing: false, track: 6, image_title: "Dark Castle", dirty: false }, FddStatus { present: true, ejected: true, motor: false, writing: false, track: 4, image_title: "", dirty: false }, FddStatus { present: false, ejected: true, motor: false, writing: false, track: 4, image_title: "", dirty: false }], model: Plus, speed: Uncapped, scsi: [None, None, None, None, None, None, None] } [2025-09-21T08:11:28Z INFO single] Event: NextCode [2025-09-21T08:11:28Z INFO single] Event: Status: EmulatorStatus { regs: RegisterFile { d: [1, 74, 9, 1347437320, 345087, 121856, 238, 16], a: [932, 2147489698, 4203454, 13994, 14546, 0, 13202], usp: 0, isp: 4171236, sr: RegisterSR { 0: 8192, sr: 8192, ccr: 0, c: false, v: false, z: false, n: false, x: false, int_prio_mask: 0, m: false, supervisor: true, trace: false }, pc: 4203552, dfc: 0, sfc: 0, vbr: 0, caar: 0, cacr: RegisterCACR { 0: 0, e: false, f: false, ce: false, c: false }, msp: 0, fpu: FpuRegisterFile { fp: [Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }], fpcr: RegisterFPCR { 0: 0, mode: 0, rnd: 0, prec: 0, exc: FpuExceptions { 0: 0, inex1: false, inex2: false, dz: false, unfl: false, ovfl: false, operr: false, snan: false, bsun: false } }, fpsr: RegisterFPSR { 0: 0, fpcc: 0, fpcc_nan: false, fpcc_i: false, fpcc_z: false, fpcc_n: false, quotient: 0, quotient_s: false, exs: FpuExceptions { 0: 0, inex1: false, inex2: false, dz: false, unfl: false, ovfl: false, operr: false, snan: false, bsun: false }, aexc: FpuAccruedExceptions { 0: 0, inex: false, dz: false, unfl: false, ovfl: false, iop: false, snan: false, bsun: false } }, fpiar: 0 }, pmmu: PmmuRegisterFile { crp: RootPointerReg { 0: 0, lu: false, limit: 0, sg: false, dt: 0, table_addr: 0 }, srp: RootPointerReg { 0: 0, lu: false, limit: 0, sg: false, dt: 0, table_addr: 0 }, drp: RootPointerReg { 0: 0, lu: false, limit: 0, sg: false, dt: 0, table_addr: 0 }, pcsr: RegisterPCSR { 0: 0, ta: 0, flush: false, lw: false }, cal: AccessLevelReg { 0: 0, al: 0 }, val: AccessLevelReg { 0: 0, al: 0 }, scc: 0, ac: AccessControlReg { 0: 0, mc: false, alc: 0, mds: 0 }, tc: TcReg { 0: 0, enable: false, sre: false, fcl: false, ps: 0, is: 0, tia: 0, tib: 0, tic: 0, tid: 0 }, psr: RegisterPSR { 0: 0, bus_error: false, limit_violation: false, supervisor_violation: false, access_level_violatiom: false, write_protected: false, invalid: false, modified: false, gate: false, globally_shared: false, level_number: 0 }, last_desc: 0 } }, running: true, breakpoints: [], cycles: 188508358, fdd: [FddStatus { present: true, ejected: false, motor: true, writing: false, track: 23, image_title: "Dark Castle", dirty: false }, FddStatus { present: true, ejected: true, motor: false, writing: false, track: 4, image_title: "", dirty: false }, FddStatus { present: false, ejected: true, motor: false, writing: false, track: 4, image_title: "", dirty: false }], model: Plus, speed: Uncapped, scsi: [None, None, None, None, None, None, None] } [2025-09-21T08:11:28Z INFO single] Event: NextCode [2025-09-21T08:11:29Z INFO single] Event: Status: EmulatorStatus { regs: RegisterFile { d: [4294967232, 0, 0, 191, 4294836521, 97, 26, 132], a: [14247, 776, 4295899, 4296238, 14678527, 15728638, 10485758], usp: 0, isp: 4171114, sr: RegisterSR { 0: 8960, sr: 8960, ccr: 0, c: false, v: false, z: false, n: false, x: false, int_prio_mask: 3, m: false, supervisor: true, trace: false }, pc: 4296074, dfc: 0, sfc: 0, vbr: 0, caar: 0, cacr: RegisterCACR { 0: 0, e: false, f: false, ce: false, c: false }, msp: 0, fpu: FpuRegisterFile { fp: [Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }], fpcr: RegisterFPCR { 0: 0, mode: 0, rnd: 0, prec: 0, exc: FpuExceptions { 0: 0, inex1: false, inex2: false, dz: false, unfl: false, ovfl: false, operr: false, snan: false, bsun: false } }, fpsr: RegisterFPSR { 0: 0, fpcc: 0, fpcc_nan: false, fpcc_i: false, fpcc_z: false, fpcc_n: false, quotient: 0, quotient_s: false, exs: FpuExceptions { 0: 0, inex1: false, inex2: false, dz: false, unfl: false, ovfl: false, operr: false, snan: false, bsun: false }, aexc: FpuAccruedExceptions { 0: 0, inex: false, dz: false, unfl: false, ovfl: false, iop: false, snan: false, bsun: false } }, fpiar: 0 }, pmmu: PmmuRegisterFile { crp: RootPointerReg { 0: 0, lu: false, limit: 0, sg: false, dt: 0, table_addr: 0 }, srp: RootPointerReg { 0: 0, lu: false, limit: 0, sg: false, dt: 0, table_addr: 0 }, drp: RootPointerReg { 0: 0, lu: false, limit: 0, sg: false, dt: 0, table_addr: 0 }, pcsr: RegisterPCSR { 0: 0, ta: 0, flush: false, lw: false }, cal: AccessLevelReg { 0: 0, al: 0 }, val: AccessLevelReg { 0: 0, al: 0 }, scc: 0, ac: AccessControlReg { 0: 0, mc: false, alc: 0, mds: 0 }, tc: TcReg { 0: 0, enable: false, sre: false, fcl: false, ps: 0, is: 0, tia: 0, tib: 0, tic: 0, tid: 0 }, psr: RegisterPSR { 0: 0, bus_error: false, limit_violation: false, supervisor_violation: false, access_level_violatiom: false, write_protected: false, invalid: false, modified: false, gate: false, globally_shared: false, level_number: 0 }, last_desc: 0 } }, running: true, breakpoints: [], cycles: 197246742, fdd: [FddStatus { present: true, ejected: false, motor: true, writing: false, track: 25, image_title: "Dark Castle", dirty: false }, FddStatus { present: true, ejected: true, motor: false, writing: false, track: 4, image_title: "", dirty: false }, FddStatus { present: false, ejected: true, motor: false, writing: false, track: 4, image_title: "", dirty: false }], model: Plus, speed: Uncapped, scsi: [None, None, None, None, None, None, None] } [2025-09-21T08:11:29Z INFO single] Event: NextCode [2025-09-21T08:11:29Z INFO single] Event: Status: EmulatorStatus { regs: RegisterFile { d: [4294967232, 100, 85, 2, 4294836314, 83, 243, 3], a: [35636, 776, 4295899, 4296238, 14678527, 15728638, 10485758], usp: 0, isp: 4171114, sr: RegisterSR { 0: 8977, sr: 8977, ccr: 17, c: true, v: false, z: false, n: false, x: true, int_prio_mask: 3, m: false, supervisor: true, trace: false }, pc: 4296108, dfc: 0, sfc: 0, vbr: 0, caar: 0, cacr: RegisterCACR { 0: 0, e: false, f: false, ce: false, c: false }, msp: 0, fpu: FpuRegisterFile { fp: [Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }], fpcr: RegisterFPCR { 0: 0, mode: 0, rnd: 0, prec: 0, exc: FpuExceptions { 0: 0, inex1: false, inex2: false, dz: false, unfl: false, ovfl: false, operr: false, snan: false, bsun: false } }, fpsr: RegisterFPSR { 0: 0, fpcc: 0, fpcc_nan: false, fpcc_i: false, fpcc_z: false, fpcc_n: false, quotient: 0, quotient_s: false, exs: FpuExceptions { 0: 0, inex1: false, inex2: false, dz: false, unfl: false, ovfl: false, operr: false, snan: false, bsun: false }, aexc: FpuAccruedExceptions { 0: 0, inex: false, dz: false, unfl: false, ovfl: false, iop: false, snan: false, bsun: false } }, fpiar: 0 }, pmmu: PmmuRegisterFile { crp: RootPointerReg { 0: 0, lu: false, limit: 0, sg: false, dt: 0, table_addr: 0 }, srp: RootPointerReg { 0: 0, lu: false, limit: 0, sg: false, dt: 0, table_addr: 0 }, drp: RootPointerReg { 0: 0, lu: false, limit: 0, sg: false, dt: 0, table_addr: 0 }, pcsr: RegisterPCSR { 0: 0, ta: 0, flush: false, lw: false }, cal: AccessLevelReg { 0: 0, al: 0 }, val: AccessLevelReg { 0: 0, al: 0 }, scc: 0, ac: AccessControlReg { 0: 0, mc: false, alc: 0, mds: 0 }, tc: TcReg { 0: 0, enable: false, sre: false, fcl: false, ps: 0, is: 0, tia: 0, tib: 0, tic: 0, tid: 0 }, psr: RegisterPSR { 0: 0, bus_error: false, limit_violation: false, supervisor_violation: false, access_level_violatiom: false, write_protected: false, invalid: false, modified: false, gate: false, globally_shared: false, level_number: 0 }, last_desc: 0 } }, running: true, breakpoints: [], cycles: 205500012, fdd: [FddStatus { present: true, ejected: false, motor: true, writing: false, track: 30, image_title: "Dark Castle", dirty: false }, FddStatus { present: true, ejected: true, motor: false, writing: false, track: 4, image_title: "", dirty: false }, FddStatus { present: false, ejected: true, motor: false, writing: false, track: 4, image_title: "", dirty: false }], model: Plus, speed: Uncapped, scsi: [None, None, None, None, None, None, None] } [2025-09-21T08:11:29Z INFO single] Event: NextCode [2025-09-21T08:11:30Z INFO single] Event: Status: EmulatorStatus { regs: RegisterFile { d: [139, 74, 7, 170, 228, 212, 252, 232], a: [4204004, 15720958, 776, 4296238, 4293634, 15728638, 10485758], usp: 0, isp: 4171072, sr: RegisterSR { 0: 8468, sr: 8468, ccr: 20, c: false, v: false, z: true, n: false, x: true, int_prio_mask: 1, m: false, supervisor: true, trace: false }, pc: 4204030, dfc: 0, sfc: 0, vbr: 0, caar: 0, cacr: RegisterCACR { 0: 0, e: false, f: false, ce: false, c: false }, msp: 0, fpu: FpuRegisterFile { fp: [Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }], fpcr: RegisterFPCR { 0: 0, mode: 0, rnd: 0, prec: 0, exc: FpuExceptions { 0: 0, inex1: false, inex2: false, dz: false, unfl: false, ovfl: false, operr: false, snan: false, bsun: false } }, fpsr: RegisterFPSR { 0: 0, fpcc: 0, fpcc_nan: false, fpcc_i: false, fpcc_z: false, fpcc_n: false, quotient: 0, quotient_s: false, exs: FpuExceptions { 0: 0, inex1: false, inex2: false, dz: false, unfl: false, ovfl: false, operr: false, snan: false, bsun: false }, aexc: FpuAccruedExceptions { 0: 0, inex: false, dz: false, unfl: false, ovfl: false, iop: false, snan: false, bsun: false } }, fpiar: 0 }, pmmu: PmmuRegisterFile { crp: RootPointerReg { 0: 0, lu: false, limit: 0, sg: false, dt: 0, table_addr: 0 }, srp: RootPointerReg { 0: 0, lu: false, limit: 0, sg: false, dt: 0, table_addr: 0 }, drp: RootPointerReg { 0: 0, lu: false, limit: 0, sg: false, dt: 0, table_addr: 0 }, pcsr: RegisterPCSR { 0: 0, ta: 0, flush: false, lw: false }, cal: AccessLevelReg { 0: 0, al: 0 }, val: AccessLevelReg { 0: 0, al: 0 }, scc: 0, ac: AccessControlReg { 0: 0, mc: false, alc: 0, mds: 0 }, tc: TcReg { 0: 0, enable: false, sre: false, fcl: false, ps: 0, is: 0, tia: 0, tib: 0, tic: 0, tid: 0 }, psr: RegisterPSR { 0: 0, bus_error: false, limit_violation: false, supervisor_violation: false, access_level_violatiom: false, write_protected: false, invalid: false, modified: false, gate: false, globally_shared: false, level_number: 0 }, last_desc: 0 } }, running: true, breakpoints: [], cycles: 211815808, fdd: [FddStatus { present: true, ejected: false, motor: true, writing: false, track: 34, image_title: "Dark Castle", dirty: false }, FddStatus { present: true, ejected: true, motor: false, writing: false, track: 4, image_title: "", dirty: false }, FddStatus { present: false, ejected: true, motor: false, writing: false, track: 4, image_title: "", dirty: false }], model: Plus, speed: Uncapped, scsi: [None, None, None, None, None, None, None] } [2025-09-21T08:11:30Z INFO single] Event: NextCode [2025-09-21T08:11:30Z INFO single] Event: Status: EmulatorStatus { regs: RegisterFile { d: [4294967232, 80, 64, 0, 4294836482, 255, 71, 68], a: [220165, 776, 4295899, 4296238, 14678527, 15728638, 10485758], usp: 0, isp: 4171114, sr: RegisterSR { 0: 8964, sr: 8964, ccr: 4, c: false, v: false, z: true, n: false, x: false, int_prio_mask: 3, m: false, supervisor: true, trace: false }, pc: 4296120, dfc: 0, sfc: 0, vbr: 0, caar: 0, cacr: RegisterCACR { 0: 0, e: false, f: false, ce: false, c: false }, msp: 0, fpu: FpuRegisterFile { fp: [Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }], fpcr: RegisterFPCR { 0: 0, mode: 0, rnd: 0, prec: 0, exc: FpuExceptions { 0: 0, inex1: false, inex2: false, dz: false, unfl: false, ovfl: false, operr: false, snan: false, bsun: false } }, fpsr: RegisterFPSR { 0: 0, fpcc: 0, fpcc_nan: false, fpcc_i: false, fpcc_z: false, fpcc_n: false, quotient: 0, quotient_s: false, exs: FpuExceptions { 0: 0, inex1: false, inex2: false, dz: false, unfl: false, ovfl: false, operr: false, snan: false, bsun: false }, aexc: FpuAccruedExceptions { 0: 0, inex: false, dz: false, unfl: false, ovfl: false, iop: false, snan: false, bsun: false } }, fpiar: 0 }, pmmu: PmmuRegisterFile { crp: RootPointerReg { 0: 0, lu: false, limit: 0, sg: false, dt: 0, table_addr: 0 }, srp: RootPointerReg { 0: 0, lu: false, limit: 0, sg: false, dt: 0, table_addr: 0 }, drp: RootPointerReg { 0: 0, lu: false, limit: 0, sg: false, dt: 0, table_addr: 0 }, pcsr: RegisterPCSR { 0: 0, ta: 0, flush: false, lw: false }, cal: AccessLevelReg { 0: 0, al: 0 }, val: AccessLevelReg { 0: 0, al: 0 }, scc: 0, ac: AccessControlReg { 0: 0, mc: false, alc: 0, mds: 0 }, tc: TcReg { 0: 0, enable: false, sre: false, fcl: false, ps: 0, is: 0, tia: 0, tib: 0, tic: 0, tid: 0 }, psr: RegisterPSR { 0: 0, bus_error: false, limit_violation: false, supervisor_violation: false, access_level_violatiom: false, write_protected: false, invalid: false, modified: false, gate: false, globally_shared: false, level_number: 0 }, last_desc: 0 } }, running: true, breakpoints: [], cycles: 220143726, fdd: [FddStatus { present: true, ejected: false, motor: true, writing: false, track: 40, image_title: "Dark Castle", dirty: false }, FddStatus { present: true, ejected: true, motor: false, writing: false, track: 4, image_title: "", dirty: false }, FddStatus { present: false, ejected: true, motor: false, writing: false, track: 4, image_title: "", dirty: false }], model: Plus, speed: Uncapped, scsi: [None, None, None, None, None, None, None] } [2025-09-21T08:11:30Z INFO single] Event: NextCode [2025-09-21T08:11:31Z INFO single] Event: Status: EmulatorStatus { regs: RegisterFile { d: [0, 6144, 4194304, 117, 8191, 63488, 4294967295, 20], a: [2, 4236706, 4134946, 62, 4135274, 4175940, 4134864], usp: 0, isp: 4134746, sr: RegisterSR { 0: 8192, sr: 8192, ccr: 0, c: false, v: false, z: false, n: false, x: false, int_prio_mask: 0, m: false, supervisor: true, trace: false }, pc: 4236708, dfc: 0, sfc: 0, vbr: 0, caar: 0, cacr: RegisterCACR { 0: 0, e: false, f: false, ce: false, c: false }, msp: 0, fpu: FpuRegisterFile { fp: [Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }], fpcr: RegisterFPCR { 0: 0, mode: 0, rnd: 0, prec: 0, exc: FpuExceptions { 0: 0, inex1: false, inex2: false, dz: false, unfl: false, ovfl: false, operr: false, snan: false, bsun: false } }, fpsr: RegisterFPSR { 0: 0, fpcc: 0, fpcc_nan: false, fpcc_i: false, fpcc_z: false, fpcc_n: false, quotient: 0, quotient_s: false, exs: FpuExceptions { 0: 0, inex1: false, inex2: false, dz: false, unfl: false, ovfl: false, operr: false, snan: false, bsun: false }, aexc: FpuAccruedExceptions { 0: 0, inex: false, dz: false, unfl: false, ovfl: false, iop: false, snan: false, bsun: false } }, fpiar: 0 }, pmmu: PmmuRegisterFile { crp: RootPointerReg { 0: 0, lu: false, limit: 0, sg: false, dt: 0, table_addr: 0 }, srp: RootPointerReg { 0: 0, lu: false, limit: 0, sg: false, dt: 0, table_addr: 0 }, drp: RootPointerReg { 0: 0, lu: false, limit: 0, sg: false, dt: 0, table_addr: 0 }, pcsr: RegisterPCSR { 0: 0, ta: 0, flush: false, lw: false }, cal: AccessLevelReg { 0: 0, al: 0 }, val: AccessLevelReg { 0: 0, al: 0 }, scc: 0, ac: AccessControlReg { 0: 0, mc: false, alc: 0, mds: 0 }, tc: TcReg { 0: 0, enable: false, sre: false, fcl: false, ps: 0, is: 0, tia: 0, tib: 0, tic: 0, tid: 0 }, psr: RegisterPSR { 0: 0, bus_error: false, limit_violation: false, supervisor_violation: false, access_level_violatiom: false, write_protected: false, invalid: false, modified: false, gate: false, globally_shared: false, level_number: 0 }, last_desc: 0 } }, running: true, breakpoints: [], cycles: 226665456, fdd: [FddStatus { present: true, ejected: false, motor: true, writing: false, track: 66, image_title: "Dark Castle", dirty: false }, FddStatus { present: true, ejected: true, motor: false, writing: false, track: 4, image_title: "", dirty: false }, FddStatus { present: false, ejected: true, motor: false, writing: false, track: 4, image_title: "", dirty: false }], model: Plus, speed: Uncapped, scsi: [None, None, None, None, None, None, None] } [2025-09-21T08:11:31Z INFO single] Event: NextCode [2025-09-21T08:11:31Z WARN snow_core::cpu_m68k::bus] Unaligned access: address 0000000D [2025-09-21T08:11:31Z DEBUG snow_core::cpu_m68k::cpu] Address error: read = true, address = 0000000D PC = 00408F74 [2025-09-21T08:11:31Z WARN snow_core::cpu_m68k::bus] Unaligned access: address 0000005B [2025-09-21T08:11:31Z DEBUG snow_core::cpu_m68k::cpu] Address error: read = true, address = 0000005B PC = 0040E450 [2025-09-21T08:11:31Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00902B66 [2025-09-21T08:11:31Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00902B67 [2025-09-21T08:11:31Z WARN snow_core::cpu_m68k::bus] Unaligned access: address F8902B67 [2025-09-21T08:11:31Z DEBUG snow_core::cpu_m68k::cpu] Address error: read = true, address = F8902B67 PC = 00409F54 [2025-09-21T08:11:31Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFFE8 [2025-09-21T08:11:31Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFFE9 [2025-09-21T08:11:31Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFFEA [2025-09-21T08:11:31Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFFEB [2025-09-21T08:11:31Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003A 00 [2025-09-21T08:11:31Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003B 00 [2025-09-21T08:11:31Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003C 00 [2025-09-21T08:11:31Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003D 00 [2025-09-21T08:11:31Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFFEC [2025-09-21T08:11:31Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFFED [2025-09-21T08:11:31Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFFEE [2025-09-21T08:11:31Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFFEF [2025-09-21T08:11:31Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003E 00 [2025-09-21T08:11:31Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003F 00 [2025-09-21T08:11:31Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80040 00 [2025-09-21T08:11:31Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80041 00 [2025-09-21T08:11:31Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80038 00 [2025-09-21T08:11:31Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80039 0B [2025-09-21T08:11:31Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFF7E [2025-09-21T08:11:31Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFF7F [2025-09-21T08:11:31Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFF80 [2025-09-21T08:11:31Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFF81 [2025-09-21T08:11:31Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80034 00 [2025-09-21T08:11:31Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80035 01 [2025-09-21T08:11:31Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80036 00 [2025-09-21T08:11:31Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80037 01 [2025-09-21T08:11:31Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80038 00 [2025-09-21T08:11:31Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80039 08 [2025-09-21T08:11:31Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003A FF [2025-09-21T08:11:31Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003B FF [2025-09-21T08:11:31Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003C FF [2025-09-21T08:11:31Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003D FF [2025-09-21T08:11:31Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003E FF [2025-09-21T08:11:31Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003F FF [2025-09-21T08:11:31Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80040 FF [2025-09-21T08:11:31Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80041 FF [2025-09-21T08:11:31Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80030 00 [2025-09-21T08:11:31Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80031 A4 [2025-09-21T08:11:31Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80032 01 [2025-09-21T08:11:31Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80033 80 [2025-09-21T08:11:31Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00FFFF50 00 [2025-09-21T08:11:31Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00FFFF51 00 [2025-09-21T08:11:31Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00FFFF52 09 [2025-09-21T08:11:31Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00FFFF53 98 [2025-09-21T08:11:31Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00FFFF54 00 [2025-09-21T08:11:31Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00FFFF55 1E [2025-09-21T08:11:31Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00FFFF56 00 [2025-09-21T08:11:31Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00FFFF57 00 [2025-09-21T08:11:31Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFF50 [2025-09-21T08:11:31Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFF51 [2025-09-21T08:11:31Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFF52 [2025-09-21T08:11:31Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFF53 [2025-09-21T08:11:31Z WARN snow_core::cpu_m68k::bus] Unaligned access: address 0000FFFF [2025-09-21T08:11:31Z DEBUG snow_core::cpu_m68k::cpu] Address error: read = true, address = 0000FFFF PC = 00408F70 [2025-09-21T08:11:31Z INFO single] Event: Status: EmulatorStatus { regs: RegisterFile { d: [25, 24, 4194304, 114, 31, 65511, 4294901784, 28], a: [2, 4236706, 4134454, 62, 4134782, 4176122, 4134372], usp: 0, isp: 4134254, sr: RegisterSR { 0: 8192, sr: 8192, ccr: 0, c: false, v: false, z: false, n: false, x: false, int_prio_mask: 0, m: false, supervisor: true, trace: false }, pc: 4236726, dfc: 0, sfc: 0, vbr: 0, caar: 0, cacr: RegisterCACR { 0: 0, e: false, f: false, ce: false, c: false }, msp: 0, fpu: FpuRegisterFile { fp: [Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }], fpcr: RegisterFPCR { 0: 0, mode: 0, rnd: 0, prec: 0, exc: FpuExceptions { 0: 0, inex1: false, inex2: false, dz: false, unfl: false, ovfl: false, operr: false, snan: false, bsun: false } }, fpsr: RegisterFPSR { 0: 0, fpcc: 0, fpcc_nan: false, fpcc_i: false, fpcc_z: false, fpcc_n: false, quotient: 0, quotient_s: false, exs: FpuExceptions { 0: 0, inex1: false, inex2: false, dz: false, unfl: false, ovfl: false, operr: false, snan: false, bsun: false }, aexc: FpuAccruedExceptions { 0: 0, inex: false, dz: false, unfl: false, ovfl: false, iop: false, snan: false, bsun: false } }, fpiar: 0 }, pmmu: PmmuRegisterFile { crp: RootPointerReg { 0: 0, lu: false, limit: 0, sg: false, dt: 0, table_addr: 0 }, srp: RootPointerReg { 0: 0, lu: false, limit: 0, sg: false, dt: 0, table_addr: 0 }, drp: RootPointerReg { 0: 0, lu: false, limit: 0, sg: false, dt: 0, table_addr: 0 }, pcsr: RegisterPCSR { 0: 0, ta: 0, flush: false, lw: false }, cal: AccessLevelReg { 0: 0, al: 0 }, val: AccessLevelReg { 0: 0, al: 0 }, scc: 0, ac: AccessControlReg { 0: 0, mc: false, alc: 0, mds: 0 }, tc: TcReg { 0: 0, enable: false, sre: false, fcl: false, ps: 0, is: 0, tia: 0, tib: 0, tic: 0, tid: 0 }, psr: RegisterPSR { 0: 0, bus_error: false, limit_violation: false, supervisor_violation: false, access_level_violatiom: false, write_protected: false, invalid: false, modified: false, gate: false, globally_shared: false, level_number: 0 }, last_desc: 0 } }, running: true, breakpoints: [], cycles: 230679064, fdd: [FddStatus { present: true, ejected: false, motor: true, writing: false, track: 66, image_title: "Dark Castle", dirty: false }, FddStatus { present: true, ejected: true, motor: false, writing: false, track: 4, image_title: "", dirty: false }, FddStatus { present: false, ejected: true, motor: false, writing: false, track: 4, image_title: "", dirty: false }], model: Plus, speed: Uncapped, scsi: [None, None, None, None, None, None, None] } [2025-09-21T08:11:31Z INFO single] Event: NextCode [2025-09-21T08:11:31Z WARN snow_core::cpu_m68k::bus] Unaligned access: address 0000005B [2025-09-21T08:11:31Z DEBUG snow_core::cpu_m68k::cpu] Address error: read = true, address = 0000005B PC = 0040E450 [2025-09-21T08:11:32Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00902B66 [2025-09-21T08:11:32Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00902B67 [2025-09-21T08:11:32Z WARN snow_core::cpu_m68k::bus] Unaligned access: address F8902B67 [2025-09-21T08:11:32Z DEBUG snow_core::cpu_m68k::cpu] Address error: read = true, address = F8902B67 PC = 00409F54 [2025-09-21T08:11:32Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFFE8 [2025-09-21T08:11:32Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFFE9 [2025-09-21T08:11:32Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFFEA [2025-09-21T08:11:32Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFFEB [2025-09-21T08:11:32Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003A 00 [2025-09-21T08:11:32Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003B 00 [2025-09-21T08:11:32Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003C 00 [2025-09-21T08:11:32Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003D 00 [2025-09-21T08:11:32Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFFEC [2025-09-21T08:11:32Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFFED [2025-09-21T08:11:32Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFFEE [2025-09-21T08:11:32Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFFEF [2025-09-21T08:11:32Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003E 00 [2025-09-21T08:11:32Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003F 00 [2025-09-21T08:11:32Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80040 00 [2025-09-21T08:11:32Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80041 00 [2025-09-21T08:11:32Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80038 00 [2025-09-21T08:11:32Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80039 0B [2025-09-21T08:11:32Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFF7E [2025-09-21T08:11:32Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFF7F [2025-09-21T08:11:32Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFF80 [2025-09-21T08:11:32Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFF81 [2025-09-21T08:11:32Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80034 00 [2025-09-21T08:11:32Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80035 01 [2025-09-21T08:11:32Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80036 00 [2025-09-21T08:11:32Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80037 01 [2025-09-21T08:11:32Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80038 00 [2025-09-21T08:11:32Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80039 08 [2025-09-21T08:11:32Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003A FF [2025-09-21T08:11:32Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003B FF [2025-09-21T08:11:32Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003C FF [2025-09-21T08:11:32Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003D FF [2025-09-21T08:11:32Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003E FF [2025-09-21T08:11:32Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003F FF [2025-09-21T08:11:32Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80040 FF [2025-09-21T08:11:32Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80041 FF [2025-09-21T08:11:32Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80030 00 [2025-09-21T08:11:32Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80031 A4 [2025-09-21T08:11:32Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80032 01 [2025-09-21T08:11:32Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80033 80 [2025-09-21T08:11:32Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00FFFF50 00 [2025-09-21T08:11:32Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00FFFF51 00 [2025-09-21T08:11:32Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00FFFF52 09 [2025-09-21T08:11:32Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00FFFF53 98 [2025-09-21T08:11:32Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00FFFF54 00 [2025-09-21T08:11:32Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00FFFF55 1E [2025-09-21T08:11:32Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00FFFF56 00 [2025-09-21T08:11:32Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00FFFF57 00 [2025-09-21T08:11:32Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFF50 [2025-09-21T08:11:32Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFF51 [2025-09-21T08:11:32Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFF52 [2025-09-21T08:11:32Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFF53 [2025-09-21T08:11:32Z WARN snow_core::cpu_m68k::bus] Unaligned access: address 0000FFFF [2025-09-21T08:11:32Z DEBUG snow_core::cpu_m68k::cpu] Address error: read = true, address = 0000FFFF PC = 00408F70 [2025-09-21T08:11:32Z INFO single] Event: Status: EmulatorStatus { regs: RegisterFile { d: [1, 24, 4194304, 81, 31, 65511, 4294901784, 28], a: [2, 4236706, 4135130, 62, 4135458, 4178170, 4135048], usp: 0, isp: 4134930, sr: RegisterSR { 0: 8192, sr: 8192, ccr: 0, c: false, v: false, z: false, n: false, x: false, int_prio_mask: 0, m: false, supervisor: true, trace: false }, pc: 4236716, dfc: 0, sfc: 0, vbr: 0, caar: 0, cacr: RegisterCACR { 0: 0, e: false, f: false, ce: false, c: false }, msp: 0, fpu: FpuRegisterFile { fp: [Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }], fpcr: RegisterFPCR { 0: 0, mode: 0, rnd: 0, prec: 0, exc: FpuExceptions { 0: 0, inex1: false, inex2: false, dz: false, unfl: false, ovfl: false, operr: false, snan: false, bsun: false } }, fpsr: RegisterFPSR { 0: 0, fpcc: 0, fpcc_nan: false, fpcc_i: false, fpcc_z: false, fpcc_n: false, quotient: 0, quotient_s: false, exs: FpuExceptions { 0: 0, inex1: false, inex2: false, dz: false, unfl: false, ovfl: false, operr: false, snan: false, bsun: false }, aexc: FpuAccruedExceptions { 0: 0, inex: false, dz: false, unfl: false, ovfl: false, iop: false, snan: false, bsun: false } }, fpiar: 0 }, pmmu: PmmuRegisterFile { crp: RootPointerReg { 0: 0, lu: false, limit: 0, sg: false, dt: 0, table_addr: 0 }, srp: RootPointerReg { 0: 0, lu: false, limit: 0, sg: false, dt: 0, table_addr: 0 }, drp: RootPointerReg { 0: 0, lu: false, limit: 0, sg: false, dt: 0, table_addr: 0 }, pcsr: RegisterPCSR { 0: 0, ta: 0, flush: false, lw: false }, cal: AccessLevelReg { 0: 0, al: 0 }, val: AccessLevelReg { 0: 0, al: 0 }, scc: 0, ac: AccessControlReg { 0: 0, mc: false, alc: 0, mds: 0 }, tc: TcReg { 0: 0, enable: false, sre: false, fcl: false, ps: 0, is: 0, tia: 0, tib: 0, tic: 0, tid: 0 }, psr: RegisterPSR { 0: 0, bus_error: false, limit_violation: false, supervisor_violation: false, access_level_violatiom: false, write_protected: false, invalid: false, modified: false, gate: false, globally_shared: false, level_number: 0 }, last_desc: 0 } }, running: true, breakpoints: [], cycles: 234198516, fdd: [FddStatus { present: true, ejected: false, motor: true, writing: false, track: 66, image_title: "Dark Castle", dirty: false }, FddStatus { present: true, ejected: true, motor: false, writing: false, track: 4, image_title: "", dirty: false }, FddStatus { present: false, ejected: true, motor: false, writing: false, track: 4, image_title: "", dirty: false }], model: Plus, speed: Uncapped, scsi: [None, None, None, None, None, None, None] } [2025-09-21T08:11:32Z INFO single] Event: NextCode [2025-09-21T08:11:32Z WARN snow_core::cpu_m68k::bus] Unaligned access: address 0000005B [2025-09-21T08:11:32Z DEBUG snow_core::cpu_m68k::cpu] Address error: read = true, address = 0000005B PC = 0040E450 [2025-09-21T08:11:32Z WARN snow_core::cpu_m68k::bus] Unaligned access: address 00000035 [2025-09-21T08:11:32Z DEBUG snow_core::cpu_m68k::cpu] Address error: read = true, address = 00000035 PC = 0040981C [2025-09-21T08:11:32Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFFE8 [2025-09-21T08:11:32Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFFE9 [2025-09-21T08:11:32Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFFEA [2025-09-21T08:11:32Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFFEB [2025-09-21T08:11:32Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003A 00 [2025-09-21T08:11:32Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003B 00 [2025-09-21T08:11:32Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003C 00 [2025-09-21T08:11:32Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003D 00 [2025-09-21T08:11:32Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFFEC [2025-09-21T08:11:32Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFFED [2025-09-21T08:11:32Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFFEE [2025-09-21T08:11:32Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFFEF [2025-09-21T08:11:32Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003E 00 [2025-09-21T08:11:32Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003F 00 [2025-09-21T08:11:32Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80040 00 [2025-09-21T08:11:32Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80041 00 [2025-09-21T08:11:32Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80038 00 [2025-09-21T08:11:32Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80039 0B [2025-09-21T08:11:32Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFF7E [2025-09-21T08:11:32Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFF7F [2025-09-21T08:11:32Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFF80 [2025-09-21T08:11:32Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFF81 [2025-09-21T08:11:32Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80034 00 [2025-09-21T08:11:32Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80035 01 [2025-09-21T08:11:32Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80036 00 [2025-09-21T08:11:32Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80037 01 [2025-09-21T08:11:32Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80038 00 [2025-09-21T08:11:32Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80039 08 [2025-09-21T08:11:32Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003A FF [2025-09-21T08:11:32Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003B FF [2025-09-21T08:11:32Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003C FF [2025-09-21T08:11:32Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003D FF [2025-09-21T08:11:32Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003E FF [2025-09-21T08:11:32Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003F FF [2025-09-21T08:11:32Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80040 FF [2025-09-21T08:11:32Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80041 FF [2025-09-21T08:11:32Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80030 00 [2025-09-21T08:11:32Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80031 A4 [2025-09-21T08:11:32Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80032 01 [2025-09-21T08:11:32Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80033 80 [2025-09-21T08:11:32Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00FFFF50 00 [2025-09-21T08:11:32Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00FFFF51 00 [2025-09-21T08:11:32Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00FFFF52 09 [2025-09-21T08:11:32Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00FFFF53 98 [2025-09-21T08:11:32Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00FFFF54 00 [2025-09-21T08:11:32Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00FFFF55 1E [2025-09-21T08:11:32Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00FFFF56 00 [2025-09-21T08:11:32Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00FFFF57 00 [2025-09-21T08:11:32Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFF50 [2025-09-21T08:11:32Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFF51 [2025-09-21T08:11:32Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFF52 [2025-09-21T08:11:32Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFF53 [2025-09-21T08:11:32Z WARN snow_core::cpu_m68k::bus] Unaligned access: address 0000FFFF [2025-09-21T08:11:32Z DEBUG snow_core::cpu_m68k::cpu] Address error: read = true, address = 0000FFFF PC = 00408F70 [2025-09-21T08:11:32Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 007EFFFE [2025-09-21T08:11:32Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 007EFFFF [2025-09-21T08:11:32Z WARN snow_core::cpu_m68k::bus] Unaligned access: address 1A7EFFFF [2025-09-21T08:11:32Z DEBUG snow_core::cpu_m68k::cpu] Address error: read = true, address = 1A7EFFFF PC = 00408C50 [2025-09-21T08:11:32Z INFO single] Event: Status: EmulatorStatus { regs: RegisterFile { d: [486643, 4, 320, 3145759, 458752, 13, 0, 2], a: [4228152, 29309, 136, 62, 2688677800, 4182474, 4135388], usp: 0, isp: 4135144, sr: RegisterSR { 0: 8209, sr: 8209, ccr: 17, c: true, v: false, z: false, n: false, x: true, int_prio_mask: 0, m: false, supervisor: true, trace: false }, pc: 4232124, dfc: 0, sfc: 0, vbr: 0, caar: 0, cacr: RegisterCACR { 0: 0, e: false, f: false, ce: false, c: false }, msp: 0, fpu: FpuRegisterFile { fp: [Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }], fpcr: RegisterFPCR { 0: 0, mode: 0, rnd: 0, prec: 0, exc: FpuExceptions { 0: 0, inex1: false, inex2: false, dz: false, unfl: false, ovfl: false, operr: false, snan: false, bsun: false } }, fpsr: RegisterFPSR { 0: 0, fpcc: 0, fpcc_nan: false, fpcc_i: false, fpcc_z: false, fpcc_n: false, quotient: 0, quotient_s: false, exs: FpuExceptions { 0: 0, inex1: false, inex2: false, dz: false, unfl: false, ovfl: false, operr: false, snan: false, bsun: false }, aexc: FpuAccruedExceptions { 0: 0, inex: false, dz: false, unfl: false, ovfl: false, iop: false, snan: false, bsun: false } }, fpiar: 0 }, pmmu: PmmuRegisterFile { crp: RootPointerReg { 0: 0, lu: false, limit: 0, sg: false, dt: 0, table_addr: 0 }, srp: RootPointerReg { 0: 0, lu: false, limit: 0, sg: false, dt: 0, table_addr: 0 }, drp: RootPointerReg { 0: 0, lu: false, limit: 0, sg: false, dt: 0, table_addr: 0 }, pcsr: RegisterPCSR { 0: 0, ta: 0, flush: false, lw: false }, cal: AccessLevelReg { 0: 0, al: 0 }, val: AccessLevelReg { 0: 0, al: 0 }, scc: 0, ac: AccessControlReg { 0: 0, mc: false, alc: 0, mds: 0 }, tc: TcReg { 0: 0, enable: false, sre: false, fcl: false, ps: 0, is: 0, tia: 0, tib: 0, tic: 0, tid: 0 }, psr: RegisterPSR { 0: 0, bus_error: false, limit_violation: false, supervisor_violation: false, access_level_violatiom: false, write_protected: false, invalid: false, modified: false, gate: false, globally_shared: false, level_number: 0 }, last_desc: 0 } }, running: true, breakpoints: [], cycles: 237553010, fdd: [FddStatus { present: true, ejected: false, motor: true, writing: false, track: 66, image_title: "Dark Castle", dirty: false }, FddStatus { present: true, ejected: true, motor: false, writing: false, track: 4, image_title: "", dirty: false }, FddStatus { present: false, ejected: true, motor: false, writing: false, track: 4, image_title: "", dirty: false }], model: Plus, speed: Uncapped, scsi: [None, None, None, None, None, None, None] } [2025-09-21T08:11:32Z INFO single] Event: NextCode [2025-09-21T08:11:32Z WARN snow_core::cpu_m68k::bus] Unaligned access: address D34DB70B [2025-09-21T08:11:32Z DEBUG snow_core::cpu_m68k::cpu] Address error: read = true, address = D34DB70B PC = 0040B036 [2025-09-21T08:11:33Z WARN snow_core::cpu_m68k::bus] Unaligned access: address 0000005B [2025-09-21T08:11:33Z DEBUG snow_core::cpu_m68k::cpu] Address error: read = true, address = 0000005B PC = 0040E450 [2025-09-21T08:11:33Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00401176 00 [2025-09-21T08:11:33Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00401177 40 [2025-09-21T08:11:33Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00401178 11 [2025-09-21T08:11:33Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00401179 30 [2025-09-21T08:11:33Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 0040117A 00 [2025-09-21T08:11:33Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 0040117B 40 [2025-09-21T08:11:33Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 0040117C 11 [2025-09-21T08:11:33Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 0040117D 32 [2025-09-21T08:11:33Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00401174 00 [2025-09-21T08:11:33Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00401175 0B [2025-09-21T08:11:33Z WARN snow_core::cpu_m68k::bus] Unaligned access: address 3F390047 [2025-09-21T08:11:33Z DEBUG snow_core::cpu_m68k::cpu] Address error: read = true, address = 3F390047 PC = 00409F54 [2025-09-21T08:11:33Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFFE8 [2025-09-21T08:11:33Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFFE9 [2025-09-21T08:11:33Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFFEA [2025-09-21T08:11:33Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFFEB [2025-09-21T08:11:33Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003A 00 [2025-09-21T08:11:33Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003B 00 [2025-09-21T08:11:33Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003C 00 [2025-09-21T08:11:33Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003D 00 [2025-09-21T08:11:33Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFFEC [2025-09-21T08:11:33Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFFED [2025-09-21T08:11:33Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFFEE [2025-09-21T08:11:33Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFFEF [2025-09-21T08:11:33Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003E 00 [2025-09-21T08:11:33Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003F 00 [2025-09-21T08:11:33Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80040 00 [2025-09-21T08:11:33Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80041 00 [2025-09-21T08:11:33Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80038 00 [2025-09-21T08:11:33Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80039 0B [2025-09-21T08:11:33Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFF7E [2025-09-21T08:11:33Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFF7F [2025-09-21T08:11:33Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFF80 [2025-09-21T08:11:33Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFF81 [2025-09-21T08:11:33Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80034 00 [2025-09-21T08:11:33Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80035 01 [2025-09-21T08:11:33Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80036 00 [2025-09-21T08:11:33Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80037 01 [2025-09-21T08:11:33Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80038 00 [2025-09-21T08:11:33Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80039 08 [2025-09-21T08:11:33Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003A FF [2025-09-21T08:11:33Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003B FF [2025-09-21T08:11:33Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003C FF [2025-09-21T08:11:33Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003D FF [2025-09-21T08:11:33Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003E FF [2025-09-21T08:11:33Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003F FF [2025-09-21T08:11:33Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80040 FF [2025-09-21T08:11:33Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80041 FF [2025-09-21T08:11:33Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80030 00 [2025-09-21T08:11:33Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80031 A4 [2025-09-21T08:11:33Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80032 01 [2025-09-21T08:11:33Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80033 80 [2025-09-21T08:11:33Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00FFFF50 00 [2025-09-21T08:11:33Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00FFFF51 00 [2025-09-21T08:11:33Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00FFFF52 09 [2025-09-21T08:11:33Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00FFFF53 98 [2025-09-21T08:11:33Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00FFFF54 00 [2025-09-21T08:11:33Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00FFFF55 1E [2025-09-21T08:11:33Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00FFFF56 00 [2025-09-21T08:11:33Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00FFFF57 00 [2025-09-21T08:11:33Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFF50 [2025-09-21T08:11:33Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFF51 [2025-09-21T08:11:33Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFF52 [2025-09-21T08:11:33Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFF53 [2025-09-21T08:11:33Z WARN snow_core::cpu_m68k::bus] Unaligned access: address 0000FFFF [2025-09-21T08:11:33Z DEBUG snow_core::cpu_m68k::cpu] Address error: read = true, address = 0000FFFF PC = 00408F70 [2025-09-21T08:11:33Z INFO single] Event: Status: EmulatorStatus { regs: RegisterFile { d: [4480, 8, 320, 6553663, 524288, 7, 0, 1], a: [4228152, 28847, 136, 62, 2688678348, 4178000, 4134694], usp: 0, isp: 4134450, sr: RegisterSR { 0: 8192, sr: 8192, ccr: 0, c: false, v: false, z: false, n: false, x: false, int_prio_mask: 0, m: false, supervisor: true, trace: false }, pc: 4232112, dfc: 0, sfc: 0, vbr: 0, caar: 0, cacr: RegisterCACR { 0: 0, e: false, f: false, ce: false, c: false }, msp: 0, fpu: FpuRegisterFile { fp: [Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }], fpcr: RegisterFPCR { 0: 0, mode: 0, rnd: 0, prec: 0, exc: FpuExceptions { 0: 0, inex1: false, inex2: false, dz: false, unfl: false, ovfl: false, operr: false, snan: false, bsun: false } }, fpsr: RegisterFPSR { 0: 0, fpcc: 0, fpcc_nan: false, fpcc_i: false, fpcc_z: false, fpcc_n: false, quotient: 0, quotient_s: false, exs: FpuExceptions { 0: 0, inex1: false, inex2: false, dz: false, unfl: false, ovfl: false, operr: false, snan: false, bsun: false }, aexc: FpuAccruedExceptions { 0: 0, inex: false, dz: false, unfl: false, ovfl: false, iop: false, snan: false, bsun: false } }, fpiar: 0 }, pmmu: PmmuRegisterFile { crp: RootPointerReg { 0: 0, lu: false, limit: 0, sg: false, dt: 0, table_addr: 0 }, srp: RootPointerReg { 0: 0, lu: false, limit: 0, sg: false, dt: 0, table_addr: 0 }, drp: RootPointerReg { 0: 0, lu: false, limit: 0, sg: false, dt: 0, table_addr: 0 }, pcsr: RegisterPCSR { 0: 0, ta: 0, flush: false, lw: false }, cal: AccessLevelReg { 0: 0, al: 0 }, val: AccessLevelReg { 0: 0, al: 0 }, scc: 0, ac: AccessControlReg { 0: 0, mc: false, alc: 0, mds: 0 }, tc: TcReg { 0: 0, enable: false, sre: false, fcl: false, ps: 0, is: 0, tia: 0, tib: 0, tic: 0, tid: 0 }, psr: RegisterPSR { 0: 0, bus_error: false, limit_violation: false, supervisor_violation: false, access_level_violatiom: false, write_protected: false, invalid: false, modified: false, gate: false, globally_shared: false, level_number: 0 }, last_desc: 0 } }, running: true, breakpoints: [], cycles: 241548388, fdd: [FddStatus { present: true, ejected: false, motor: true, writing: false, track: 66, image_title: "Dark Castle", dirty: false }, FddStatus { present: true, ejected: true, motor: false, writing: false, track: 4, image_title: "", dirty: false }, FddStatus { present: false, ejected: true, motor: false, writing: false, track: 4, image_title: "", dirty: false }], model: Plus, speed: Uncapped, scsi: [None, None, None, None, None, None, None] } [2025-09-21T08:11:33Z INFO single] Event: NextCode [2025-09-21T08:11:33Z WARN snow_core::cpu_m68k::bus] Unaligned access: address 0000005B [2025-09-21T08:11:33Z DEBUG snow_core::cpu_m68k::cpu] Address error: read = true, address = 0000005B PC = 0040E450 [2025-09-21T08:11:33Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFFFE [2025-09-21T08:11:33Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFFFF [2025-09-21T08:11:33Z WARN snow_core::cpu_m68k::bus] Unaligned access: address 00FFFFFF [2025-09-21T08:11:33Z DEBUG snow_core::cpu_m68k::cpu] Address error: read = true, address = 00FFFFFF PC = 00FFFFFB [2025-09-21T08:11:33Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFFE8 [2025-09-21T08:11:33Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFFE9 [2025-09-21T08:11:33Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFFEA [2025-09-21T08:11:33Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFFEB [2025-09-21T08:11:33Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003A 00 [2025-09-21T08:11:33Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003B 00 [2025-09-21T08:11:33Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003C 00 [2025-09-21T08:11:33Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003D 00 [2025-09-21T08:11:33Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFFEC [2025-09-21T08:11:33Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFFED [2025-09-21T08:11:33Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFFEE [2025-09-21T08:11:33Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFFEF [2025-09-21T08:11:33Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003E 00 [2025-09-21T08:11:33Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003F 00 [2025-09-21T08:11:33Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80040 00 [2025-09-21T08:11:33Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80041 00 [2025-09-21T08:11:33Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80038 00 [2025-09-21T08:11:33Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80039 0B [2025-09-21T08:11:33Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFF7E [2025-09-21T08:11:33Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFF7F [2025-09-21T08:11:33Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFF80 [2025-09-21T08:11:33Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFF81 [2025-09-21T08:11:33Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80034 00 [2025-09-21T08:11:33Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80035 01 [2025-09-21T08:11:33Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80036 00 [2025-09-21T08:11:33Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80037 01 [2025-09-21T08:11:33Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80038 00 [2025-09-21T08:11:33Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80039 08 [2025-09-21T08:11:33Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003A FF [2025-09-21T08:11:33Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003B FF [2025-09-21T08:11:33Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003C FF [2025-09-21T08:11:33Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003D FF [2025-09-21T08:11:33Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003E FF [2025-09-21T08:11:33Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003F FF [2025-09-21T08:11:33Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80040 FF [2025-09-21T08:11:33Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80041 FF [2025-09-21T08:11:33Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80030 00 [2025-09-21T08:11:33Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80031 A4 [2025-09-21T08:11:33Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80032 01 [2025-09-21T08:11:33Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80033 80 [2025-09-21T08:11:33Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00FFFF50 00 [2025-09-21T08:11:33Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00FFFF51 00 [2025-09-21T08:11:33Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00FFFF52 09 [2025-09-21T08:11:33Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00FFFF53 98 [2025-09-21T08:11:33Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00FFFF54 00 [2025-09-21T08:11:33Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00FFFF55 1E [2025-09-21T08:11:33Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00FFFF56 00 [2025-09-21T08:11:33Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00FFFF57 00 [2025-09-21T08:11:33Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFF50 [2025-09-21T08:11:33Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFF51 [2025-09-21T08:11:33Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFF52 [2025-09-21T08:11:33Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFF53 [2025-09-21T08:11:33Z WARN snow_core::cpu_m68k::bus] Unaligned access: address 0000FFFF [2025-09-21T08:11:33Z DEBUG snow_core::cpu_m68k::cpu] Address error: read = true, address = 0000FFFF PC = 00408F70 [2025-09-21T08:11:33Z INFO single] Event: Status: EmulatorStatus { regs: RegisterFile { d: [4294901767, 14, 9, 15, 21, 0, 3481324800, 163], a: [4228152, 4181958, 0, 4135720, 4228906, 4134780, 4135792], usp: 0, isp: 4135414, sr: RegisterSR { 0: 8192, sr: 8192, ccr: 0, c: false, v: false, z: false, n: false, x: false, int_prio_mask: 0, m: false, supervisor: true, trace: false }, pc: 4228774, dfc: 0, sfc: 0, vbr: 0, caar: 0, cacr: RegisterCACR { 0: 0, e: false, f: false, ce: false, c: false }, msp: 0, fpu: FpuRegisterFile { fp: [Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }], fpcr: RegisterFPCR { 0: 0, mode: 0, rnd: 0, prec: 0, exc: FpuExceptions { 0: 0, inex1: false, inex2: false, dz: false, unfl: false, ovfl: false, operr: false, snan: false, bsun: false } }, fpsr: RegisterFPSR { 0: 0, fpcc: 0, fpcc_nan: false, fpcc_i: false, fpcc_z: false, fpcc_n: false, quotient: 0, quotient_s: false, exs: FpuExceptions { 0: 0, inex1: false, inex2: false, dz: false, unfl: false, ovfl: false, operr: false, snan: false, bsun: false }, aexc: FpuAccruedExceptions { 0: 0, inex: false, dz: false, unfl: false, ovfl: false, iop: false, snan: false, bsun: false } }, fpiar: 0 }, pmmu: PmmuRegisterFile { crp: RootPointerReg { 0: 0, lu: false, limit: 0, sg: false, dt: 0, table_addr: 0 }, srp: RootPointerReg { 0: 0, lu: false, limit: 0, sg: false, dt: 0, table_addr: 0 }, drp: RootPointerReg { 0: 0, lu: false, limit: 0, sg: false, dt: 0, table_addr: 0 }, pcsr: RegisterPCSR { 0: 0, ta: 0, flush: false, lw: false }, cal: AccessLevelReg { 0: 0, al: 0 }, val: AccessLevelReg { 0: 0, al: 0 }, scc: 0, ac: AccessControlReg { 0: 0, mc: false, alc: 0, mds: 0 }, tc: TcReg { 0: 0, enable: false, sre: false, fcl: false, ps: 0, is: 0, tia: 0, tib: 0, tic: 0, tid: 0 }, psr: RegisterPSR { 0: 0, bus_error: false, limit_violation: false, supervisor_violation: false, access_level_violatiom: false, write_protected: false, invalid: false, modified: false, gate: false, globally_shared: false, level_number: 0 }, last_desc: 0 } }, running: true, breakpoints: [], cycles: 244590098, fdd: [FddStatus { present: true, ejected: false, motor: true, writing: false, track: 66, image_title: "Dark Castle", dirty: false }, FddStatus { present: true, ejected: true, motor: false, writing: false, track: 4, image_title: "", dirty: false }, FddStatus { present: false, ejected: true, motor: false, writing: false, track: 4, image_title: "", dirty: false }], model: Plus, speed: Uncapped, scsi: [None, None, None, None, None, None, None] } [2025-09-21T08:11:33Z INFO single] Event: NextCode [2025-09-21T08:11:34Z WARN snow_core::cpu_m68k::bus] Unaligned access: address 0000005B [2025-09-21T08:11:34Z DEBUG snow_core::cpu_m68k::cpu] Address error: read = true, address = 0000005B PC = 0040E450 [2025-09-21T08:11:34Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFFFE [2025-09-21T08:11:34Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFFFF [2025-09-21T08:11:34Z WARN snow_core::cpu_m68k::bus] Unaligned access: address 00FFFFFF [2025-09-21T08:11:34Z DEBUG snow_core::cpu_m68k::cpu] Address error: read = true, address = 00FFFFFF PC = 00FFFFFB [2025-09-21T08:11:34Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFFE8 [2025-09-21T08:11:34Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFFE9 [2025-09-21T08:11:34Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFFEA [2025-09-21T08:11:34Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFFEB [2025-09-21T08:11:34Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003A 00 [2025-09-21T08:11:34Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003B 00 [2025-09-21T08:11:34Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003C 00 [2025-09-21T08:11:34Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003D 00 [2025-09-21T08:11:34Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFFEC [2025-09-21T08:11:34Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFFED [2025-09-21T08:11:34Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFFEE [2025-09-21T08:11:34Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFFEF [2025-09-21T08:11:34Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003E 00 [2025-09-21T08:11:34Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003F 00 [2025-09-21T08:11:34Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80040 00 [2025-09-21T08:11:34Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80041 00 [2025-09-21T08:11:34Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80038 00 [2025-09-21T08:11:34Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80039 0B [2025-09-21T08:11:34Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFF7E [2025-09-21T08:11:34Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFF7F [2025-09-21T08:11:34Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFF80 [2025-09-21T08:11:34Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFF81 [2025-09-21T08:11:34Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80034 00 [2025-09-21T08:11:34Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80035 01 [2025-09-21T08:11:34Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80036 00 [2025-09-21T08:11:34Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80037 01 [2025-09-21T08:11:34Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80038 00 [2025-09-21T08:11:34Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80039 08 [2025-09-21T08:11:34Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003A FF [2025-09-21T08:11:34Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003B FF [2025-09-21T08:11:34Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003C FF [2025-09-21T08:11:34Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003D FF [2025-09-21T08:11:34Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003E FF [2025-09-21T08:11:34Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003F FF [2025-09-21T08:11:34Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80040 FF [2025-09-21T08:11:34Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80041 FF [2025-09-21T08:11:34Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80030 00 [2025-09-21T08:11:34Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80031 A4 [2025-09-21T08:11:34Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80032 01 [2025-09-21T08:11:34Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80033 80 [2025-09-21T08:11:34Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00FFFF50 00 [2025-09-21T08:11:34Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00FFFF51 00 [2025-09-21T08:11:34Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00FFFF52 09 [2025-09-21T08:11:34Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00FFFF53 98 [2025-09-21T08:11:34Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00FFFF54 00 [2025-09-21T08:11:34Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00FFFF55 1E [2025-09-21T08:11:34Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00FFFF56 00 [2025-09-21T08:11:34Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00FFFF57 00 [2025-09-21T08:11:34Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFF50 [2025-09-21T08:11:34Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFF51 [2025-09-21T08:11:34Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFF52 [2025-09-21T08:11:34Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFF53 [2025-09-21T08:11:34Z WARN snow_core::cpu_m68k::bus] Unaligned access: address 0000FFFF [2025-09-21T08:11:34Z DEBUG snow_core::cpu_m68k::cpu] Address error: read = true, address = 0000FFFF PC = 00408F70 [2025-09-21T08:11:34Z WARN snow_core::cpu_m68k::bus] Unaligned access: address 0000005B [2025-09-21T08:11:34Z DEBUG snow_core::cpu_m68k::cpu] Address error: read = true, address = 0000005B PC = 0040E450 [2025-09-21T08:11:34Z INFO single] Event: Status: EmulatorStatus { regs: RegisterFile { d: [1047724262, 478, 5, 3145803, 458752, 2, 0, 65535], a: [2688678558, 29309, 136, 64, 2688678198, 4182664, 4135352], usp: 0, isp: 4135108, sr: RegisterSR { 0: 8192, sr: 8192, ccr: 0, c: false, v: false, z: false, n: false, x: false, int_prio_mask: 0, m: false, supervisor: true, trace: false }, pc: 4231858, dfc: 0, sfc: 0, vbr: 0, caar: 0, cacr: RegisterCACR { 0: 0, e: false, f: false, ce: false, c: false }, msp: 0, fpu: FpuRegisterFile { fp: [Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }], fpcr: RegisterFPCR { 0: 0, mode: 0, rnd: 0, prec: 0, exc: FpuExceptions { 0: 0, inex1: false, inex2: false, dz: false, unfl: false, ovfl: false, operr: false, snan: false, bsun: false } }, fpsr: RegisterFPSR { 0: 0, fpcc: 0, fpcc_nan: false, fpcc_i: false, fpcc_z: false, fpcc_n: false, quotient: 0, quotient_s: false, exs: FpuExceptions { 0: 0, inex1: false, inex2: false, dz: false, unfl: false, ovfl: false, operr: false, snan: false, bsun: false }, aexc: FpuAccruedExceptions { 0: 0, inex: false, dz: false, unfl: false, ovfl: false, iop: false, snan: false, bsun: false } }, fpiar: 0 }, pmmu: PmmuRegisterFile { crp: RootPointerReg { 0: 0, lu: false, limit: 0, sg: false, dt: 0, table_addr: 0 }, srp: RootPointerReg { 0: 0, lu: false, limit: 0, sg: false, dt: 0, table_addr: 0 }, drp: RootPointerReg { 0: 0, lu: false, limit: 0, sg: false, dt: 0, table_addr: 0 }, pcsr: RegisterPCSR { 0: 0, ta: 0, flush: false, lw: false }, cal: AccessLevelReg { 0: 0, al: 0 }, val: AccessLevelReg { 0: 0, al: 0 }, scc: 0, ac: AccessControlReg { 0: 0, mc: false, alc: 0, mds: 0 }, tc: TcReg { 0: 0, enable: false, sre: false, fcl: false, ps: 0, is: 0, tia: 0, tib: 0, tic: 0, tid: 0 }, psr: RegisterPSR { 0: 0, bus_error: false, limit_violation: false, supervisor_violation: false, access_level_violatiom: false, write_protected: false, invalid: false, modified: false, gate: false, globally_shared: false, level_number: 0 }, last_desc: 0 } }, running: true, breakpoints: [], cycles: 248223580, fdd: [FddStatus { present: true, ejected: false, motor: true, writing: false, track: 66, image_title: "Dark Castle", dirty: false }, FddStatus { present: true, ejected: true, motor: false, writing: false, track: 4, image_title: "", dirty: false }, FddStatus { present: false, ejected: true, motor: false, writing: false, track: 4, image_title: "", dirty: false }], model: Plus, speed: Uncapped, scsi: [None, None, None, None, None, None, None] } [2025-09-21T08:11:34Z INFO single] Event: NextCode [2025-09-21T08:11:34Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFFFE [2025-09-21T08:11:34Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFFFF [2025-09-21T08:11:34Z WARN snow_core::cpu_m68k::bus] Unaligned access: address 00FFFFFF [2025-09-21T08:11:34Z DEBUG snow_core::cpu_m68k::cpu] Address error: read = true, address = 00FFFFFF PC = 00FFFFFB [2025-09-21T08:11:34Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFFE8 [2025-09-21T08:11:34Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFFE9 [2025-09-21T08:11:34Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFFEA [2025-09-21T08:11:34Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFFEB [2025-09-21T08:11:34Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003A 00 [2025-09-21T08:11:34Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003B 00 [2025-09-21T08:11:34Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003C 00 [2025-09-21T08:11:34Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003D 00 [2025-09-21T08:11:34Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFFEC [2025-09-21T08:11:34Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFFED [2025-09-21T08:11:34Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFFEE [2025-09-21T08:11:34Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFFEF [2025-09-21T08:11:34Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003E 00 [2025-09-21T08:11:34Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003F 00 [2025-09-21T08:11:34Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80040 00 [2025-09-21T08:11:34Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80041 00 [2025-09-21T08:11:34Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80038 00 [2025-09-21T08:11:34Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80039 0B [2025-09-21T08:11:34Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFF7E [2025-09-21T08:11:34Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFF7F [2025-09-21T08:11:34Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFF80 [2025-09-21T08:11:34Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFF81 [2025-09-21T08:11:34Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80034 00 [2025-09-21T08:11:34Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80035 01 [2025-09-21T08:11:34Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80036 00 [2025-09-21T08:11:34Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80037 01 [2025-09-21T08:11:34Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80038 00 [2025-09-21T08:11:34Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80039 08 [2025-09-21T08:11:34Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003A FF [2025-09-21T08:11:34Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003B FF [2025-09-21T08:11:34Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003C FF [2025-09-21T08:11:34Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003D FF [2025-09-21T08:11:34Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003E FF [2025-09-21T08:11:34Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003F FF [2025-09-21T08:11:34Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80040 FF [2025-09-21T08:11:34Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80041 FF [2025-09-21T08:11:34Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80030 00 [2025-09-21T08:11:34Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80031 A4 [2025-09-21T08:11:34Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80032 01 [2025-09-21T08:11:34Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80033 80 [2025-09-21T08:11:34Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00FFFF50 00 [2025-09-21T08:11:34Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00FFFF51 00 [2025-09-21T08:11:34Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00FFFF52 09 [2025-09-21T08:11:34Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00FFFF53 98 [2025-09-21T08:11:34Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00FFFF54 00 [2025-09-21T08:11:34Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00FFFF55 1E [2025-09-21T08:11:34Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00FFFF56 00 [2025-09-21T08:11:34Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00FFFF57 00 [2025-09-21T08:11:34Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFF50 [2025-09-21T08:11:34Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFF51 [2025-09-21T08:11:34Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFF52 [2025-09-21T08:11:34Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFF53 [2025-09-21T08:11:34Z WARN snow_core::cpu_m68k::bus] Unaligned access: address 0000FFFF [2025-09-21T08:11:34Z DEBUG snow_core::cpu_m68k::cpu] Address error: read = true, address = 0000FFFF PC = 00408F70 [2025-09-21T08:11:34Z WARN snow_core::cpu_m68k::bus] Unaligned access: address 0000005B [2025-09-21T08:11:34Z DEBUG snow_core::cpu_m68k::cpu] Address error: read = true, address = 0000005B PC = 0040E450 [2025-09-21T08:11:34Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFFFE [2025-09-21T08:11:34Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFFFF [2025-09-21T08:11:34Z WARN snow_core::cpu_m68k::bus] Unaligned access: address 00FFFFFF [2025-09-21T08:11:34Z DEBUG snow_core::cpu_m68k::cpu] Address error: read = true, address = 00FFFFFF PC = 00FFFFFB [2025-09-21T08:11:34Z INFO single] Event: Status: EmulatorStatus { regs: RegisterFile { d: [65537, 0, 16, 3145728, 0, 0, 6, 28762], a: [4227822, 2180, 29258, 29272, 327680, 4135822, 4135480], usp: 0, isp: 4135476, sr: RegisterSR { 0: 8192, sr: 8192, ccr: 0, c: false, v: false, z: false, n: false, x: false, int_prio_mask: 0, m: false, supervisor: true, trace: false }, pc: 4199418, dfc: 0, sfc: 0, vbr: 0, caar: 0, cacr: RegisterCACR { 0: 0, e: false, f: false, ce: false, c: false }, msp: 0, fpu: FpuRegisterFile { fp: [Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }], fpcr: RegisterFPCR { 0: 0, mode: 0, rnd: 0, prec: 0, exc: FpuExceptions { 0: 0, inex1: false, inex2: false, dz: false, unfl: false, ovfl: false, operr: false, snan: false, bsun: false } }, fpsr: RegisterFPSR { 0: 0, fpcc: 0, fpcc_nan: false, fpcc_i: false, fpcc_z: false, fpcc_n: false, quotient: 0, quotient_s: false, exs: FpuExceptions { 0: 0, inex1: false, inex2: false, dz: false, unfl: false, ovfl: false, operr: false, snan: false, bsun: false }, aexc: FpuAccruedExceptions { 0: 0, inex: false, dz: false, unfl: false, ovfl: false, iop: false, snan: false, bsun: false } }, fpiar: 0 }, pmmu: PmmuRegisterFile { crp: RootPointerReg { 0: 0, lu: false, limit: 0, sg: false, dt: 0, table_addr: 0 }, srp: RootPointerReg { 0: 0, lu: false, limit: 0, sg: false, dt: 0, table_addr: 0 }, drp: RootPointerReg { 0: 0, lu: false, limit: 0, sg: false, dt: 0, table_addr: 0 }, pcsr: RegisterPCSR { 0: 0, ta: 0, flush: false, lw: false }, cal: AccessLevelReg { 0: 0, al: 0 }, val: AccessLevelReg { 0: 0, al: 0 }, scc: 0, ac: AccessControlReg { 0: 0, mc: false, alc: 0, mds: 0 }, tc: TcReg { 0: 0, enable: false, sre: false, fcl: false, ps: 0, is: 0, tia: 0, tib: 0, tic: 0, tid: 0 }, psr: RegisterPSR { 0: 0, bus_error: false, limit_violation: false, supervisor_violation: false, access_level_violatiom: false, write_protected: false, invalid: false, modified: false, gate: false, globally_shared: false, level_number: 0 }, last_desc: 0 } }, running: true, breakpoints: [], cycles: 252004328, fdd: [FddStatus { present: true, ejected: false, motor: true, writing: false, track: 66, image_title: "Dark Castle", dirty: false }, FddStatus { present: true, ejected: true, motor: false, writing: false, track: 4, image_title: "", dirty: false }, FddStatus { present: false, ejected: true, motor: false, writing: false, track: 4, image_title: "", dirty: false }], model: Plus, speed: Uncapped, scsi: [None, None, None, None, None, None, None] } [2025-09-21T08:11:34Z INFO single] Event: NextCode [2025-09-21T08:11:35Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFFE8 [2025-09-21T08:11:35Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFFE9 [2025-09-21T08:11:35Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFFEA [2025-09-21T08:11:35Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFFEB [2025-09-21T08:11:35Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003A 00 [2025-09-21T08:11:35Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003B 00 [2025-09-21T08:11:35Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003C 00 [2025-09-21T08:11:35Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003D 00 [2025-09-21T08:11:35Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFFEC [2025-09-21T08:11:35Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFFED [2025-09-21T08:11:35Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFFEE [2025-09-21T08:11:35Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFFEF [2025-09-21T08:11:35Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003E 00 [2025-09-21T08:11:35Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003F 00 [2025-09-21T08:11:35Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80040 00 [2025-09-21T08:11:35Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80041 00 [2025-09-21T08:11:35Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80038 00 [2025-09-21T08:11:35Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80039 0B [2025-09-21T08:11:35Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFF7E [2025-09-21T08:11:35Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFF7F [2025-09-21T08:11:35Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFF80 [2025-09-21T08:11:35Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFF81 [2025-09-21T08:11:35Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80034 00 [2025-09-21T08:11:35Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80035 01 [2025-09-21T08:11:35Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80036 00 [2025-09-21T08:11:35Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80037 01 [2025-09-21T08:11:35Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80038 00 [2025-09-21T08:11:35Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80039 08 [2025-09-21T08:11:35Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003A FF [2025-09-21T08:11:35Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003B FF [2025-09-21T08:11:35Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003C FF [2025-09-21T08:11:35Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003D FF [2025-09-21T08:11:35Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003E FF [2025-09-21T08:11:35Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003F FF [2025-09-21T08:11:35Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80040 FF [2025-09-21T08:11:35Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80041 FF [2025-09-21T08:11:35Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80030 00 [2025-09-21T08:11:35Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80031 A4 [2025-09-21T08:11:35Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80032 01 [2025-09-21T08:11:35Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80033 80 [2025-09-21T08:11:35Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00FFFF50 00 [2025-09-21T08:11:35Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00FFFF51 00 [2025-09-21T08:11:35Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00FFFF52 09 [2025-09-21T08:11:35Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00FFFF53 98 [2025-09-21T08:11:35Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00FFFF54 00 [2025-09-21T08:11:35Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00FFFF55 1E [2025-09-21T08:11:35Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00FFFF56 00 [2025-09-21T08:11:35Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00FFFF57 00 [2025-09-21T08:11:35Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFF50 [2025-09-21T08:11:35Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFF51 [2025-09-21T08:11:35Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFF52 [2025-09-21T08:11:35Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFF53 [2025-09-21T08:11:35Z WARN snow_core::cpu_m68k::bus] Unaligned access: address 0000FFFF [2025-09-21T08:11:35Z DEBUG snow_core::cpu_m68k::cpu] Address error: read = true, address = 0000FFFF PC = 00408F70 [2025-09-21T08:11:35Z WARN snow_core::cpu_m68k::bus] Unaligned access: address 0000005B [2025-09-21T08:11:35Z DEBUG snow_core::cpu_m68k::cpu] Address error: read = true, address = 0000005B PC = 0040E450 [2025-09-21T08:11:35Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFFFE [2025-09-21T08:11:35Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFFFF [2025-09-21T08:11:35Z WARN snow_core::cpu_m68k::bus] Unaligned access: address 00FFFFFF [2025-09-21T08:11:35Z DEBUG snow_core::cpu_m68k::cpu] Address error: read = true, address = 00FFFFFF PC = 00FFFFFB [2025-09-21T08:11:35Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFFE8 [2025-09-21T08:11:35Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFFE9 [2025-09-21T08:11:35Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFFEA [2025-09-21T08:11:35Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFFEB [2025-09-21T08:11:35Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003A 00 [2025-09-21T08:11:35Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003B 00 [2025-09-21T08:11:35Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003C 00 [2025-09-21T08:11:35Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003D 00 [2025-09-21T08:11:35Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFFEC [2025-09-21T08:11:35Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFFED [2025-09-21T08:11:35Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFFEE [2025-09-21T08:11:35Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFFEF [2025-09-21T08:11:35Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003E 00 [2025-09-21T08:11:35Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003F 00 [2025-09-21T08:11:35Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80040 00 [2025-09-21T08:11:35Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80041 00 [2025-09-21T08:11:35Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80038 00 [2025-09-21T08:11:35Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80039 0B [2025-09-21T08:11:35Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFF7E [2025-09-21T08:11:35Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFF7F [2025-09-21T08:11:35Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFF80 [2025-09-21T08:11:35Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFF81 [2025-09-21T08:11:35Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80034 00 [2025-09-21T08:11:35Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80035 01 [2025-09-21T08:11:35Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80036 00 [2025-09-21T08:11:35Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80037 01 [2025-09-21T08:11:35Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80038 00 [2025-09-21T08:11:35Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80039 08 [2025-09-21T08:11:35Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003A FF [2025-09-21T08:11:35Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003B FF [2025-09-21T08:11:35Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003C FF [2025-09-21T08:11:35Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003D FF [2025-09-21T08:11:35Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003E FF [2025-09-21T08:11:35Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003F FF [2025-09-21T08:11:35Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80040 FF [2025-09-21T08:11:35Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80041 FF [2025-09-21T08:11:35Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80030 00 [2025-09-21T08:11:35Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80031 A4 [2025-09-21T08:11:35Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80032 01 [2025-09-21T08:11:35Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80033 80 [2025-09-21T08:11:35Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00FFFF50 00 [2025-09-21T08:11:35Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00FFFF51 00 [2025-09-21T08:11:35Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00FFFF52 09 [2025-09-21T08:11:35Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00FFFF53 98 [2025-09-21T08:11:35Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00FFFF54 00 [2025-09-21T08:11:35Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00FFFF55 1E [2025-09-21T08:11:35Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00FFFF56 00 [2025-09-21T08:11:35Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00FFFF57 00 [2025-09-21T08:11:35Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFF50 [2025-09-21T08:11:35Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFF51 [2025-09-21T08:11:35Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFF52 [2025-09-21T08:11:35Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFF53 [2025-09-21T08:11:35Z WARN snow_core::cpu_m68k::bus] Unaligned access: address 0000FFFF [2025-09-21T08:11:35Z DEBUG snow_core::cpu_m68k::cpu] Address error: read = true, address = 0000FFFF PC = 00408F70 [2025-09-21T08:11:35Z INFO single] Event: Status: EmulatorStatus { regs: RegisterFile { d: [38912, 6144, 4194304, 36, 8191, 59391, 4294907904, 24], a: [2, 4236706, 4134852, 62, 4135180, 4181124, 4134770], usp: 0, isp: 4134652, sr: RegisterSR { 0: 8192, sr: 8192, ccr: 0, c: false, v: false, z: false, n: false, x: false, int_prio_mask: 0, m: false, supervisor: true, trace: false }, pc: 4236714, dfc: 0, sfc: 0, vbr: 0, caar: 0, cacr: RegisterCACR { 0: 0, e: false, f: false, ce: false, c: false }, msp: 0, fpu: FpuRegisterFile { fp: [Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }], fpcr: RegisterFPCR { 0: 0, mode: 0, rnd: 0, prec: 0, exc: FpuExceptions { 0: 0, inex1: false, inex2: false, dz: false, unfl: false, ovfl: false, operr: false, snan: false, bsun: false } }, fpsr: RegisterFPSR { 0: 0, fpcc: 0, fpcc_nan: false, fpcc_i: false, fpcc_z: false, fpcc_n: false, quotient: 0, quotient_s: false, exs: FpuExceptions { 0: 0, inex1: false, inex2: false, dz: false, unfl: false, ovfl: false, operr: false, snan: false, bsun: false }, aexc: FpuAccruedExceptions { 0: 0, inex: false, dz: false, unfl: false, ovfl: false, iop: false, snan: false, bsun: false } }, fpiar: 0 }, pmmu: PmmuRegisterFile { crp: RootPointerReg { 0: 0, lu: false, limit: 0, sg: false, dt: 0, table_addr: 0 }, srp: RootPointerReg { 0: 0, lu: false, limit: 0, sg: false, dt: 0, table_addr: 0 }, drp: RootPointerReg { 0: 0, lu: false, limit: 0, sg: false, dt: 0, table_addr: 0 }, pcsr: RegisterPCSR { 0: 0, ta: 0, flush: false, lw: false }, cal: AccessLevelReg { 0: 0, al: 0 }, val: AccessLevelReg { 0: 0, al: 0 }, scc: 0, ac: AccessControlReg { 0: 0, mc: false, alc: 0, mds: 0 }, tc: TcReg { 0: 0, enable: false, sre: false, fcl: false, ps: 0, is: 0, tia: 0, tib: 0, tic: 0, tid: 0 }, psr: RegisterPSR { 0: 0, bus_error: false, limit_violation: false, supervisor_violation: false, access_level_violatiom: false, write_protected: false, invalid: false, modified: false, gate: false, globally_shared: false, level_number: 0 }, last_desc: 0 } }, running: true, breakpoints: [], cycles: 255374188, fdd: [FddStatus { present: true, ejected: false, motor: true, writing: false, track: 66, image_title: "Dark Castle", dirty: false }, FddStatus { present: true, ejected: true, motor: false, writing: false, track: 4, image_title: "", dirty: false }, FddStatus { present: false, ejected: true, motor: false, writing: false, track: 4, image_title: "", dirty: false }], model: Plus, speed: Uncapped, scsi: [None, None, None, None, None, None, None] } [2025-09-21T08:11:35Z INFO single] Event: NextCode [2025-09-21T08:11:35Z WARN snow_core::cpu_m68k::bus] Unaligned access: address 0000005B [2025-09-21T08:11:35Z DEBUG snow_core::cpu_m68k::cpu] Address error: read = true, address = 0000005B PC = 0040E450 [2025-09-21T08:11:35Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFFFE [2025-09-21T08:11:35Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFFFF [2025-09-21T08:11:35Z WARN snow_core::cpu_m68k::bus] Unaligned access: address 00FFFFFF [2025-09-21T08:11:35Z DEBUG snow_core::cpu_m68k::cpu] Address error: read = true, address = 00FFFFFF PC = 00FFFFFB [2025-09-21T08:11:35Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFFE8 [2025-09-21T08:11:35Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFFE9 [2025-09-21T08:11:35Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFFEA [2025-09-21T08:11:35Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFFEB [2025-09-21T08:11:35Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003A 00 [2025-09-21T08:11:35Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003B 00 [2025-09-21T08:11:35Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003C 00 [2025-09-21T08:11:35Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003D 00 [2025-09-21T08:11:35Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFFEC [2025-09-21T08:11:35Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFFED [2025-09-21T08:11:35Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFFEE [2025-09-21T08:11:35Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFFEF [2025-09-21T08:11:35Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003E 00 [2025-09-21T08:11:35Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003F 00 [2025-09-21T08:11:35Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80040 00 [2025-09-21T08:11:35Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80041 00 [2025-09-21T08:11:35Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80038 00 [2025-09-21T08:11:35Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80039 0B [2025-09-21T08:11:35Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFF7E [2025-09-21T08:11:35Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFF7F [2025-09-21T08:11:35Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFF80 [2025-09-21T08:11:35Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFF81 [2025-09-21T08:11:35Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80034 00 [2025-09-21T08:11:35Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80035 01 [2025-09-21T08:11:35Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80036 00 [2025-09-21T08:11:35Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80037 01 [2025-09-21T08:11:35Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80038 00 [2025-09-21T08:11:35Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80039 08 [2025-09-21T08:11:35Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003A FF [2025-09-21T08:11:35Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003B FF [2025-09-21T08:11:35Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003C FF [2025-09-21T08:11:35Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003D FF [2025-09-21T08:11:35Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003E FF [2025-09-21T08:11:35Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003F FF [2025-09-21T08:11:35Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80040 FF [2025-09-21T08:11:35Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80041 FF [2025-09-21T08:11:35Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80030 00 [2025-09-21T08:11:35Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80031 A4 [2025-09-21T08:11:35Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80032 01 [2025-09-21T08:11:35Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80033 80 [2025-09-21T08:11:35Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00FFFF50 00 [2025-09-21T08:11:35Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00FFFF51 00 [2025-09-21T08:11:35Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00FFFF52 09 [2025-09-21T08:11:35Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00FFFF53 98 [2025-09-21T08:11:35Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00FFFF54 00 [2025-09-21T08:11:35Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00FFFF55 1E [2025-09-21T08:11:35Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00FFFF56 00 [2025-09-21T08:11:35Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00FFFF57 00 [2025-09-21T08:11:35Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFF50 [2025-09-21T08:11:35Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFF51 [2025-09-21T08:11:35Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFF52 [2025-09-21T08:11:35Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFF53 [2025-09-21T08:11:35Z WARN snow_core::cpu_m68k::bus] Unaligned access: address 0000FFFF [2025-09-21T08:11:35Z DEBUG snow_core::cpu_m68k::cpu] Address error: read = true, address = 0000FFFF PC = 00408F70 [2025-09-21T08:11:35Z INFO single] Event: Status: EmulatorStatus { regs: RegisterFile { d: [2113961728, 0, 12, 3276800, 0, 0, 5, 28762], a: [4135026, 2132, 29258, 29272, 0, 4135122, 4134780], usp: 0, isp: 4135824, sr: RegisterSR { 0: 8192, sr: 8192, ccr: 0, c: false, v: false, z: false, n: false, x: false, int_prio_mask: 0, m: false, supervisor: true, trace: false }, pc: 4202016, dfc: 0, sfc: 0, vbr: 0, caar: 0, cacr: RegisterCACR { 0: 0, e: false, f: false, ce: false, c: false }, msp: 0, fpu: FpuRegisterFile { fp: [Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }], fpcr: RegisterFPCR { 0: 0, mode: 0, rnd: 0, prec: 0, exc: FpuExceptions { 0: 0, inex1: false, inex2: false, dz: false, unfl: false, ovfl: false, operr: false, snan: false, bsun: false } }, fpsr: RegisterFPSR { 0: 0, fpcc: 0, fpcc_nan: false, fpcc_i: false, fpcc_z: false, fpcc_n: false, quotient: 0, quotient_s: false, exs: FpuExceptions { 0: 0, inex1: false, inex2: false, dz: false, unfl: false, ovfl: false, operr: false, snan: false, bsun: false }, aexc: FpuAccruedExceptions { 0: 0, inex: false, dz: false, unfl: false, ovfl: false, iop: false, snan: false, bsun: false } }, fpiar: 0 }, pmmu: PmmuRegisterFile { crp: RootPointerReg { 0: 0, lu: false, limit: 0, sg: false, dt: 0, table_addr: 0 }, srp: RootPointerReg { 0: 0, lu: false, limit: 0, sg: false, dt: 0, table_addr: 0 }, drp: RootPointerReg { 0: 0, lu: false, limit: 0, sg: false, dt: 0, table_addr: 0 }, pcsr: RegisterPCSR { 0: 0, ta: 0, flush: false, lw: false }, cal: AccessLevelReg { 0: 0, al: 0 }, val: AccessLevelReg { 0: 0, al: 0 }, scc: 0, ac: AccessControlReg { 0: 0, mc: false, alc: 0, mds: 0 }, tc: TcReg { 0: 0, enable: false, sre: false, fcl: false, ps: 0, is: 0, tia: 0, tib: 0, tic: 0, tid: 0 }, psr: RegisterPSR { 0: 0, bus_error: false, limit_violation: false, supervisor_violation: false, access_level_violatiom: false, write_protected: false, invalid: false, modified: false, gate: false, globally_shared: false, level_number: 0 }, last_desc: 0 } }, running: true, breakpoints: [], cycles: 258935018, fdd: [FddStatus { present: true, ejected: false, motor: true, writing: false, track: 66, image_title: "Dark Castle", dirty: false }, FddStatus { present: true, ejected: true, motor: false, writing: false, track: 4, image_title: "", dirty: false }, FddStatus { present: false, ejected: true, motor: false, writing: false, track: 4, image_title: "", dirty: false }], model: Plus, speed: Uncapped, scsi: [None, None, None, None, None, None, None] } [2025-09-21T08:11:35Z INFO single] Event: NextCode [2025-09-21T08:11:35Z WARN snow_core::cpu_m68k::bus] Unaligned access: address 0000005B [2025-09-21T08:11:35Z DEBUG snow_core::cpu_m68k::cpu] Address error: read = true, address = 0000005B PC = 0040E450 [2025-09-21T08:11:36Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFFFE [2025-09-21T08:11:36Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFFFF [2025-09-21T08:11:36Z WARN snow_core::cpu_m68k::bus] Unaligned access: address 00FFFFFF [2025-09-21T08:11:36Z DEBUG snow_core::cpu_m68k::cpu] Address error: read = true, address = 00FFFFFF PC = 00FFFFFB [2025-09-21T08:11:36Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFFE8 [2025-09-21T08:11:36Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFFE9 [2025-09-21T08:11:36Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFFEA [2025-09-21T08:11:36Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFFEB [2025-09-21T08:11:36Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003A 00 [2025-09-21T08:11:36Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003B 00 [2025-09-21T08:11:36Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003C 00 [2025-09-21T08:11:36Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003D 00 [2025-09-21T08:11:36Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFFEC [2025-09-21T08:11:36Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFFED [2025-09-21T08:11:36Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFFEE [2025-09-21T08:11:36Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFFEF [2025-09-21T08:11:36Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003E 00 [2025-09-21T08:11:36Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003F 00 [2025-09-21T08:11:36Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80040 00 [2025-09-21T08:11:36Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80041 00 [2025-09-21T08:11:36Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80038 00 [2025-09-21T08:11:36Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80039 0B [2025-09-21T08:11:36Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFF7E [2025-09-21T08:11:36Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFF7F [2025-09-21T08:11:36Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFF80 [2025-09-21T08:11:36Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFF81 [2025-09-21T08:11:36Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80034 00 [2025-09-21T08:11:36Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80035 01 [2025-09-21T08:11:36Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80036 00 [2025-09-21T08:11:36Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80037 01 [2025-09-21T08:11:36Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80038 00 [2025-09-21T08:11:36Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80039 08 [2025-09-21T08:11:36Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003A FF [2025-09-21T08:11:36Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003B FF [2025-09-21T08:11:36Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003C FF [2025-09-21T08:11:36Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003D FF [2025-09-21T08:11:36Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003E FF [2025-09-21T08:11:36Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003F FF [2025-09-21T08:11:36Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80040 FF [2025-09-21T08:11:36Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80041 FF [2025-09-21T08:11:36Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80030 00 [2025-09-21T08:11:36Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80031 A4 [2025-09-21T08:11:36Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80032 01 [2025-09-21T08:11:36Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80033 80 [2025-09-21T08:11:36Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00FFFF50 00 [2025-09-21T08:11:36Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00FFFF51 00 [2025-09-21T08:11:36Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00FFFF52 09 [2025-09-21T08:11:36Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00FFFF53 98 [2025-09-21T08:11:36Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00FFFF54 00 [2025-09-21T08:11:36Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00FFFF55 1E [2025-09-21T08:11:36Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00FFFF56 00 [2025-09-21T08:11:36Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00FFFF57 00 [2025-09-21T08:11:36Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFF50 [2025-09-21T08:11:36Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFF51 [2025-09-21T08:11:36Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFF52 [2025-09-21T08:11:36Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFF53 [2025-09-21T08:11:36Z WARN snow_core::cpu_m68k::bus] Unaligned access: address 0000FFFF [2025-09-21T08:11:36Z DEBUG snow_core::cpu_m68k::cpu] Address error: read = true, address = 0000FFFF PC = 00408F70 [2025-09-21T08:11:36Z WARN snow_core::cpu_m68k::bus] Unaligned access: address 0000005B [2025-09-21T08:11:36Z DEBUG snow_core::cpu_m68k::cpu] Address error: read = true, address = 0000005B PC = 0040E450 [2025-09-21T08:11:36Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFFFE [2025-09-21T08:11:36Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFFFF [2025-09-21T08:11:36Z WARN snow_core::cpu_m68k::bus] Unaligned access: address 00FFFFFF [2025-09-21T08:11:36Z DEBUG snow_core::cpu_m68k::cpu] Address error: read = true, address = 00FFFFFF PC = 00FFFFFB [2025-09-21T08:11:36Z INFO single] Event: Status: EmulatorStatus { regs: RegisterFile { d: [3072, 262155, 192, 6553615, 393216, 9, 0, 7], a: [4228152, 28855, 136, 62, 2688677120, 4177430, 4135394], usp: 0, isp: 4135150, sr: RegisterSR { 0: 8192, sr: 8192, ccr: 0, c: false, v: false, z: false, n: false, x: false, int_prio_mask: 0, m: false, supervisor: true, trace: false }, pc: 4232112, dfc: 0, sfc: 0, vbr: 0, caar: 0, cacr: RegisterCACR { 0: 0, e: false, f: false, ce: false, c: false }, msp: 0, fpu: FpuRegisterFile { fp: [Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }], fpcr: RegisterFPCR { 0: 0, mode: 0, rnd: 0, prec: 0, exc: FpuExceptions { 0: 0, inex1: false, inex2: false, dz: false, unfl: false, ovfl: false, operr: false, snan: false, bsun: false } }, fpsr: RegisterFPSR { 0: 0, fpcc: 0, fpcc_nan: false, fpcc_i: false, fpcc_z: false, fpcc_n: false, quotient: 0, quotient_s: false, exs: FpuExceptions { 0: 0, inex1: false, inex2: false, dz: false, unfl: false, ovfl: false, operr: false, snan: false, bsun: false }, aexc: FpuAccruedExceptions { 0: 0, inex: false, dz: false, unfl: false, ovfl: false, iop: false, snan: false, bsun: false } }, fpiar: 0 }, pmmu: PmmuRegisterFile { crp: RootPointerReg { 0: 0, lu: false, limit: 0, sg: false, dt: 0, table_addr: 0 }, srp: RootPointerReg { 0: 0, lu: false, limit: 0, sg: false, dt: 0, table_addr: 0 }, drp: RootPointerReg { 0: 0, lu: false, limit: 0, sg: false, dt: 0, table_addr: 0 }, pcsr: RegisterPCSR { 0: 0, ta: 0, flush: false, lw: false }, cal: AccessLevelReg { 0: 0, al: 0 }, val: AccessLevelReg { 0: 0, al: 0 }, scc: 0, ac: AccessControlReg { 0: 0, mc: false, alc: 0, mds: 0 }, tc: TcReg { 0: 0, enable: false, sre: false, fcl: false, ps: 0, is: 0, tia: 0, tib: 0, tic: 0, tid: 0 }, psr: RegisterPSR { 0: 0, bus_error: false, limit_violation: false, supervisor_violation: false, access_level_violatiom: false, write_protected: false, invalid: false, modified: false, gate: false, globally_shared: false, level_number: 0 }, last_desc: 0 } }, running: true, breakpoints: [], cycles: 263208478, fdd: [FddStatus { present: true, ejected: false, motor: true, writing: false, track: 66, image_title: "Dark Castle", dirty: false }, FddStatus { present: true, ejected: true, motor: false, writing: false, track: 4, image_title: "", dirty: false }, FddStatus { present: false, ejected: true, motor: false, writing: false, track: 4, image_title: "", dirty: false }], model: Plus, speed: Uncapped, scsi: [None, None, None, None, None, None, None] } [2025-09-21T08:11:36Z INFO single] Event: NextCode [2025-09-21T08:11:36Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFFE8 [2025-09-21T08:11:36Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFFE9 [2025-09-21T08:11:36Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFFEA [2025-09-21T08:11:36Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFFEB [2025-09-21T08:11:36Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003A 00 [2025-09-21T08:11:36Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003B 00 [2025-09-21T08:11:36Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003C 00 [2025-09-21T08:11:36Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003D 00 [2025-09-21T08:11:36Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFFEC [2025-09-21T08:11:36Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFFED [2025-09-21T08:11:36Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFFEE [2025-09-21T08:11:36Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFFEF [2025-09-21T08:11:36Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003E 00 [2025-09-21T08:11:36Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003F 00 [2025-09-21T08:11:36Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80040 00 [2025-09-21T08:11:36Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80041 00 [2025-09-21T08:11:36Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80038 00 [2025-09-21T08:11:36Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80039 0B [2025-09-21T08:11:36Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFF7E [2025-09-21T08:11:36Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFF7F [2025-09-21T08:11:36Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFF80 [2025-09-21T08:11:36Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFF81 [2025-09-21T08:11:36Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80034 00 [2025-09-21T08:11:36Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80035 01 [2025-09-21T08:11:36Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80036 00 [2025-09-21T08:11:36Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80037 01 [2025-09-21T08:11:36Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80038 00 [2025-09-21T08:11:36Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80039 08 [2025-09-21T08:11:36Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003A FF [2025-09-21T08:11:36Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003B FF [2025-09-21T08:11:36Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003C FF [2025-09-21T08:11:36Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003D FF [2025-09-21T08:11:36Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003E FF [2025-09-21T08:11:36Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003F FF [2025-09-21T08:11:36Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80040 FF [2025-09-21T08:11:36Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80041 FF [2025-09-21T08:11:36Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80030 00 [2025-09-21T08:11:36Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80031 A4 [2025-09-21T08:11:36Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80032 01 [2025-09-21T08:11:36Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80033 80 [2025-09-21T08:11:36Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00FFFF50 00 [2025-09-21T08:11:36Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00FFFF51 00 [2025-09-21T08:11:36Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00FFFF52 09 [2025-09-21T08:11:36Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00FFFF53 98 [2025-09-21T08:11:36Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00FFFF54 00 [2025-09-21T08:11:36Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00FFFF55 1E [2025-09-21T08:11:36Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00FFFF56 00 [2025-09-21T08:11:36Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00FFFF57 00 [2025-09-21T08:11:36Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFF50 [2025-09-21T08:11:36Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFF51 [2025-09-21T08:11:36Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFF52 [2025-09-21T08:11:36Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFF53 [2025-09-21T08:11:36Z WARN snow_core::cpu_m68k::bus] Unaligned access: address 0000FFFF [2025-09-21T08:11:36Z DEBUG snow_core::cpu_m68k::cpu] Address error: read = true, address = 0000FFFF PC = 00408F70 [2025-09-21T08:11:36Z WARN snow_core::cpu_m68k::bus] Unaligned access: address 0000005B [2025-09-21T08:11:36Z DEBUG snow_core::cpu_m68k::cpu] Address error: read = true, address = 0000005B PC = 0040E450 [2025-09-21T08:11:36Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFFFE [2025-09-21T08:11:36Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFFFF [2025-09-21T08:11:36Z WARN snow_core::cpu_m68k::bus] Unaligned access: address 00FFFFFF [2025-09-21T08:11:36Z DEBUG snow_core::cpu_m68k::cpu] Address error: read = true, address = 00FFFFFF PC = 00FFFFFB [2025-09-21T08:11:36Z INFO single] Event: Status: EmulatorStatus { regs: RegisterFile { d: [1, 0, 4194304, 116, 1, 0, 4294901760, 32], a: [2, 4236774, 4236864, 60, 4135084, 4176188, 4134666], usp: 0, isp: 4134548, sr: RegisterSR { 0: 8196, sr: 8196, ccr: 4, c: false, v: false, z: true, n: false, x: false, int_prio_mask: 0, m: false, supervisor: true, trace: false }, pc: 4236796, dfc: 0, sfc: 0, vbr: 0, caar: 0, cacr: RegisterCACR { 0: 0, e: false, f: false, ce: false, c: false }, msp: 0, fpu: FpuRegisterFile { fp: [Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }], fpcr: RegisterFPCR { 0: 0, mode: 0, rnd: 0, prec: 0, exc: FpuExceptions { 0: 0, inex1: false, inex2: false, dz: false, unfl: false, ovfl: false, operr: false, snan: false, bsun: false } }, fpsr: RegisterFPSR { 0: 0, fpcc: 0, fpcc_nan: false, fpcc_i: false, fpcc_z: false, fpcc_n: false, quotient: 0, quotient_s: false, exs: FpuExceptions { 0: 0, inex1: false, inex2: false, dz: false, unfl: false, ovfl: false, operr: false, snan: false, bsun: false }, aexc: FpuAccruedExceptions { 0: 0, inex: false, dz: false, unfl: false, ovfl: false, iop: false, snan: false, bsun: false } }, fpiar: 0 }, pmmu: PmmuRegisterFile { crp: RootPointerReg { 0: 0, lu: false, limit: 0, sg: false, dt: 0, table_addr: 0 }, srp: RootPointerReg { 0: 0, lu: false, limit: 0, sg: false, dt: 0, table_addr: 0 }, drp: RootPointerReg { 0: 0, lu: false, limit: 0, sg: false, dt: 0, table_addr: 0 }, pcsr: RegisterPCSR { 0: 0, ta: 0, flush: false, lw: false }, cal: AccessLevelReg { 0: 0, al: 0 }, val: AccessLevelReg { 0: 0, al: 0 }, scc: 0, ac: AccessControlReg { 0: 0, mc: false, alc: 0, mds: 0 }, tc: TcReg { 0: 0, enable: false, sre: false, fcl: false, ps: 0, is: 0, tia: 0, tib: 0, tic: 0, tid: 0 }, psr: RegisterPSR { 0: 0, bus_error: false, limit_violation: false, supervisor_violation: false, access_level_violatiom: false, write_protected: false, invalid: false, modified: false, gate: false, globally_shared: false, level_number: 0 }, last_desc: 0 } }, running: true, breakpoints: [], cycles: 266432002, fdd: [FddStatus { present: true, ejected: false, motor: true, writing: false, track: 66, image_title: "Dark Castle", dirty: false }, FddStatus { present: true, ejected: true, motor: false, writing: false, track: 4, image_title: "", dirty: false }, FddStatus { present: false, ejected: true, motor: false, writing: false, track: 4, image_title: "", dirty: false }], model: Plus, speed: Uncapped, scsi: [None, None, None, None, None, None, None] } [2025-09-21T08:11:36Z INFO single] Event: NextCode [2025-09-21T08:11:37Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFFE8 [2025-09-21T08:11:37Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFFE9 [2025-09-21T08:11:37Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFFEA [2025-09-21T08:11:37Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFFEB [2025-09-21T08:11:37Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003A 00 [2025-09-21T08:11:37Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003B 00 [2025-09-21T08:11:37Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003C 00 [2025-09-21T08:11:37Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003D 00 [2025-09-21T08:11:37Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFFEC [2025-09-21T08:11:37Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFFED [2025-09-21T08:11:37Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFFEE [2025-09-21T08:11:37Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFFEF [2025-09-21T08:11:37Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003E 00 [2025-09-21T08:11:37Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003F 00 [2025-09-21T08:11:37Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80040 00 [2025-09-21T08:11:37Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80041 00 [2025-09-21T08:11:37Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80038 00 [2025-09-21T08:11:37Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80039 0B [2025-09-21T08:11:37Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFF7E [2025-09-21T08:11:37Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFF7F [2025-09-21T08:11:37Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFF80 [2025-09-21T08:11:37Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFF81 [2025-09-21T08:11:37Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80034 00 [2025-09-21T08:11:37Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80035 01 [2025-09-21T08:11:37Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80036 00 [2025-09-21T08:11:37Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80037 01 [2025-09-21T08:11:37Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80038 00 [2025-09-21T08:11:37Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80039 08 [2025-09-21T08:11:37Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003A FF [2025-09-21T08:11:37Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003B FF [2025-09-21T08:11:37Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003C FF [2025-09-21T08:11:37Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003D FF [2025-09-21T08:11:37Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003E FF [2025-09-21T08:11:37Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003F FF [2025-09-21T08:11:37Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80040 FF [2025-09-21T08:11:37Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80041 FF [2025-09-21T08:11:37Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80030 00 [2025-09-21T08:11:37Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80031 A4 [2025-09-21T08:11:37Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80032 01 [2025-09-21T08:11:37Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80033 80 [2025-09-21T08:11:37Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00FFFF50 00 [2025-09-21T08:11:37Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00FFFF51 00 [2025-09-21T08:11:37Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00FFFF52 09 [2025-09-21T08:11:37Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00FFFF53 98 [2025-09-21T08:11:37Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00FFFF54 00 [2025-09-21T08:11:37Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00FFFF55 1E [2025-09-21T08:11:37Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00FFFF56 00 [2025-09-21T08:11:37Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00FFFF57 00 [2025-09-21T08:11:37Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFF50 [2025-09-21T08:11:37Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFF51 [2025-09-21T08:11:37Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFF52 [2025-09-21T08:11:37Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFF53 [2025-09-21T08:11:37Z WARN snow_core::cpu_m68k::bus] Unaligned access: address 0000FFFF [2025-09-21T08:11:37Z DEBUG snow_core::cpu_m68k::cpu] Address error: read = true, address = 0000FFFF PC = 00408F70 [2025-09-21T08:11:37Z WARN snow_core::cpu_m68k::bus] Unaligned access: address 0000005B [2025-09-21T08:11:37Z DEBUG snow_core::cpu_m68k::cpu] Address error: read = true, address = 0000005B PC = 0040E450 [2025-09-21T08:11:37Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFFFE [2025-09-21T08:11:37Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFFFF [2025-09-21T08:11:37Z WARN snow_core::cpu_m68k::bus] Unaligned access: address 00FFFFFF [2025-09-21T08:11:37Z DEBUG snow_core::cpu_m68k::cpu] Address error: read = true, address = 00FFFFFF PC = 00FFFFFB [2025-09-21T08:11:37Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFFE8 [2025-09-21T08:11:37Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFFE9 [2025-09-21T08:11:37Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFFEA [2025-09-21T08:11:37Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFFEB [2025-09-21T08:11:37Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003A 00 [2025-09-21T08:11:37Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003B 00 [2025-09-21T08:11:37Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003C 00 [2025-09-21T08:11:37Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003D 00 [2025-09-21T08:11:37Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFFEC [2025-09-21T08:11:37Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFFED [2025-09-21T08:11:37Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFFEE [2025-09-21T08:11:37Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFFEF [2025-09-21T08:11:37Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003E 00 [2025-09-21T08:11:37Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003F 00 [2025-09-21T08:11:37Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80040 00 [2025-09-21T08:11:37Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80041 00 [2025-09-21T08:11:37Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80038 00 [2025-09-21T08:11:37Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80039 0B [2025-09-21T08:11:37Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFF7E [2025-09-21T08:11:37Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFF7F [2025-09-21T08:11:37Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFF80 [2025-09-21T08:11:37Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFF81 [2025-09-21T08:11:37Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80034 00 [2025-09-21T08:11:37Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80035 01 [2025-09-21T08:11:37Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80036 00 [2025-09-21T08:11:37Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80037 01 [2025-09-21T08:11:37Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80038 00 [2025-09-21T08:11:37Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80039 08 [2025-09-21T08:11:37Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003A FF [2025-09-21T08:11:37Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003B FF [2025-09-21T08:11:37Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003C FF [2025-09-21T08:11:37Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003D FF [2025-09-21T08:11:37Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003E FF [2025-09-21T08:11:37Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003F FF [2025-09-21T08:11:37Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80040 FF [2025-09-21T08:11:37Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80041 FF [2025-09-21T08:11:37Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80030 00 [2025-09-21T08:11:37Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80031 A4 [2025-09-21T08:11:37Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80032 01 [2025-09-21T08:11:37Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80033 80 [2025-09-21T08:11:37Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00FFFF50 00 [2025-09-21T08:11:37Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00FFFF51 00 [2025-09-21T08:11:37Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00FFFF52 09 [2025-09-21T08:11:37Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00FFFF53 98 [2025-09-21T08:11:37Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00FFFF54 00 [2025-09-21T08:11:37Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00FFFF55 1E [2025-09-21T08:11:37Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00FFFF56 00 [2025-09-21T08:11:37Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00FFFF57 00 [2025-09-21T08:11:37Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFF50 [2025-09-21T08:11:37Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFF51 [2025-09-21T08:11:37Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFF52 [2025-09-21T08:11:37Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFF53 [2025-09-21T08:11:37Z WARN snow_core::cpu_m68k::bus] Unaligned access: address 0000FFFF [2025-09-21T08:11:37Z DEBUG snow_core::cpu_m68k::cpu] Address error: read = true, address = 0000FFFF PC = 00408F70 [2025-09-21T08:11:37Z INFO single] Event: Status: EmulatorStatus { regs: RegisterFile { d: [65537, 0, 16, 3276800, 0, 0, 5, 28762], a: [4227822, 2180, 29258, 29272, 0, 4135122, 4134780], usp: 0, isp: 4135850, sr: RegisterSR { 0: 8192, sr: 8192, ccr: 0, c: false, v: false, z: false, n: false, x: false, int_prio_mask: 0, m: false, supervisor: true, trace: false }, pc: 4199410, dfc: 0, sfc: 0, vbr: 0, caar: 0, cacr: RegisterCACR { 0: 0, e: false, f: false, ce: false, c: false }, msp: 0, fpu: FpuRegisterFile { fp: [Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }], fpcr: RegisterFPCR { 0: 0, mode: 0, rnd: 0, prec: 0, exc: FpuExceptions { 0: 0, inex1: false, inex2: false, dz: false, unfl: false, ovfl: false, operr: false, snan: false, bsun: false } }, fpsr: RegisterFPSR { 0: 0, fpcc: 0, fpcc_nan: false, fpcc_i: false, fpcc_z: false, fpcc_n: false, quotient: 0, quotient_s: false, exs: FpuExceptions { 0: 0, inex1: false, inex2: false, dz: false, unfl: false, ovfl: false, operr: false, snan: false, bsun: false }, aexc: FpuAccruedExceptions { 0: 0, inex: false, dz: false, unfl: false, ovfl: false, iop: false, snan: false, bsun: false } }, fpiar: 0 }, pmmu: PmmuRegisterFile { crp: RootPointerReg { 0: 0, lu: false, limit: 0, sg: false, dt: 0, table_addr: 0 }, srp: RootPointerReg { 0: 0, lu: false, limit: 0, sg: false, dt: 0, table_addr: 0 }, drp: RootPointerReg { 0: 0, lu: false, limit: 0, sg: false, dt: 0, table_addr: 0 }, pcsr: RegisterPCSR { 0: 0, ta: 0, flush: false, lw: false }, cal: AccessLevelReg { 0: 0, al: 0 }, val: AccessLevelReg { 0: 0, al: 0 }, scc: 0, ac: AccessControlReg { 0: 0, mc: false, alc: 0, mds: 0 }, tc: TcReg { 0: 0, enable: false, sre: false, fcl: false, ps: 0, is: 0, tia: 0, tib: 0, tic: 0, tid: 0 }, psr: RegisterPSR { 0: 0, bus_error: false, limit_violation: false, supervisor_violation: false, access_level_violatiom: false, write_protected: false, invalid: false, modified: false, gate: false, globally_shared: false, level_number: 0 }, last_desc: 0 } }, running: true, breakpoints: [], cycles: 270494288, fdd: [FddStatus { present: true, ejected: false, motor: true, writing: false, track: 66, image_title: "Dark Castle", dirty: false }, FddStatus { present: true, ejected: true, motor: false, writing: false, track: 4, image_title: "", dirty: false }, FddStatus { present: false, ejected: true, motor: false, writing: false, track: 4, image_title: "", dirty: false }], model: Plus, speed: Uncapped, scsi: [None, None, None, None, None, None, None] } [2025-09-21T08:11:37Z INFO single] Event: NextCode [2025-09-21T08:11:37Z WARN snow_core::cpu_m68k::bus] Unaligned access: address 0000005B [2025-09-21T08:11:37Z DEBUG snow_core::cpu_m68k::cpu] Address error: read = true, address = 0000005B PC = 0040E450 [2025-09-21T08:11:37Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFFFE [2025-09-21T08:11:37Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFFFF [2025-09-21T08:11:37Z WARN snow_core::cpu_m68k::bus] Unaligned access: address 00FFFFFF [2025-09-21T08:11:37Z DEBUG snow_core::cpu_m68k::cpu] Address error: read = true, address = 00FFFFFF PC = 00FFFFFB [2025-09-21T08:11:37Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFFE8 [2025-09-21T08:11:37Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFFE9 [2025-09-21T08:11:37Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFFEA [2025-09-21T08:11:37Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFFEB [2025-09-21T08:11:37Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003A 00 [2025-09-21T08:11:37Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003B 00 [2025-09-21T08:11:37Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003C 00 [2025-09-21T08:11:37Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003D 00 [2025-09-21T08:11:37Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFFEC [2025-09-21T08:11:37Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFFED [2025-09-21T08:11:37Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFFEE [2025-09-21T08:11:37Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFFEF [2025-09-21T08:11:37Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003E 00 [2025-09-21T08:11:37Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003F 00 [2025-09-21T08:11:37Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80040 00 [2025-09-21T08:11:37Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80041 00 [2025-09-21T08:11:37Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80038 00 [2025-09-21T08:11:37Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80039 0B [2025-09-21T08:11:37Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFF7E [2025-09-21T08:11:37Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFF7F [2025-09-21T08:11:37Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFF80 [2025-09-21T08:11:37Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFF81 [2025-09-21T08:11:37Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80034 00 [2025-09-21T08:11:37Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80035 01 [2025-09-21T08:11:37Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80036 00 [2025-09-21T08:11:37Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80037 01 [2025-09-21T08:11:37Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80038 00 [2025-09-21T08:11:37Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80039 08 [2025-09-21T08:11:37Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003A FF [2025-09-21T08:11:37Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003B FF [2025-09-21T08:11:37Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003C FF [2025-09-21T08:11:37Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003D FF [2025-09-21T08:11:37Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003E FF [2025-09-21T08:11:37Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003F FF [2025-09-21T08:11:37Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80040 FF [2025-09-21T08:11:37Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80041 FF [2025-09-21T08:11:37Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80030 00 [2025-09-21T08:11:37Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80031 A4 [2025-09-21T08:11:37Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80032 01 [2025-09-21T08:11:37Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80033 80 [2025-09-21T08:11:37Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00FFFF50 00 [2025-09-21T08:11:37Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00FFFF51 00 [2025-09-21T08:11:37Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00FFFF52 09 [2025-09-21T08:11:37Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00FFFF53 98 [2025-09-21T08:11:37Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00FFFF54 00 [2025-09-21T08:11:37Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00FFFF55 1E [2025-09-21T08:11:37Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00FFFF56 00 [2025-09-21T08:11:37Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00FFFF57 00 [2025-09-21T08:11:37Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFF50 [2025-09-21T08:11:37Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFF51 [2025-09-21T08:11:37Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFF52 [2025-09-21T08:11:37Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFF53 [2025-09-21T08:11:37Z WARN snow_core::cpu_m68k::bus] Unaligned access: address 0000FFFF [2025-09-21T08:11:37Z DEBUG snow_core::cpu_m68k::cpu] Address error: read = true, address = 0000FFFF PC = 00408F70 [2025-09-21T08:11:37Z WARN snow_core::cpu_m68k::bus] Unaligned access: address 0000005B [2025-09-21T08:11:37Z DEBUG snow_core::cpu_m68k::cpu] Address error: read = true, address = 0000005B PC = 0040E450 [2025-09-21T08:11:38Z INFO single] Event: Status: EmulatorStatus { regs: RegisterFile { d: [32, 4135238, 4200416, 3145983, 0, 0, 6, 28674], a: [4134722, 484, 1016, 1016, 4135036, 4135376, 4134640], usp: 0, isp: 4134558, sr: RegisterSR { 0: 8192, sr: 8192, ccr: 0, c: false, v: false, z: false, n: false, x: false, int_prio_mask: 0, m: false, supervisor: true, trace: false }, pc: 4235912, dfc: 0, sfc: 0, vbr: 0, caar: 0, cacr: RegisterCACR { 0: 0, e: false, f: false, ce: false, c: false }, msp: 0, fpu: FpuRegisterFile { fp: [Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }], fpcr: RegisterFPCR { 0: 0, mode: 0, rnd: 0, prec: 0, exc: FpuExceptions { 0: 0, inex1: false, inex2: false, dz: false, unfl: false, ovfl: false, operr: false, snan: false, bsun: false } }, fpsr: RegisterFPSR { 0: 0, fpcc: 0, fpcc_nan: false, fpcc_i: false, fpcc_z: false, fpcc_n: false, quotient: 0, quotient_s: false, exs: FpuExceptions { 0: 0, inex1: false, inex2: false, dz: false, unfl: false, ovfl: false, operr: false, snan: false, bsun: false }, aexc: FpuAccruedExceptions { 0: 0, inex: false, dz: false, unfl: false, ovfl: false, iop: false, snan: false, bsun: false } }, fpiar: 0 }, pmmu: PmmuRegisterFile { crp: RootPointerReg { 0: 0, lu: false, limit: 0, sg: false, dt: 0, table_addr: 0 }, srp: RootPointerReg { 0: 0, lu: false, limit: 0, sg: false, dt: 0, table_addr: 0 }, drp: RootPointerReg { 0: 0, lu: false, limit: 0, sg: false, dt: 0, table_addr: 0 }, pcsr: RegisterPCSR { 0: 0, ta: 0, flush: false, lw: false }, cal: AccessLevelReg { 0: 0, al: 0 }, val: AccessLevelReg { 0: 0, al: 0 }, scc: 0, ac: AccessControlReg { 0: 0, mc: false, alc: 0, mds: 0 }, tc: TcReg { 0: 0, enable: false, sre: false, fcl: false, ps: 0, is: 0, tia: 0, tib: 0, tic: 0, tid: 0 }, psr: RegisterPSR { 0: 0, bus_error: false, limit_violation: false, supervisor_violation: false, access_level_violatiom: false, write_protected: false, invalid: false, modified: false, gate: false, globally_shared: false, level_number: 0 }, last_desc: 0 } }, running: true, breakpoints: [], cycles: 274170950, fdd: [FddStatus { present: true, ejected: false, motor: true, writing: false, track: 66, image_title: "Dark Castle", dirty: false }, FddStatus { present: true, ejected: true, motor: false, writing: false, track: 4, image_title: "", dirty: false }, FddStatus { present: false, ejected: true, motor: false, writing: false, track: 4, image_title: "", dirty: false }], model: Plus, speed: Uncapped, scsi: [None, None, None, None, None, None, None] } [2025-09-21T08:11:38Z INFO single] Event: NextCode [2025-09-21T08:11:38Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFFFE [2025-09-21T08:11:38Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFFFF [2025-09-21T08:11:38Z WARN snow_core::cpu_m68k::bus] Unaligned access: address 00FFFFFF [2025-09-21T08:11:38Z DEBUG snow_core::cpu_m68k::cpu] Address error: read = true, address = 00FFFFFF PC = 00FFFFFB [2025-09-21T08:11:38Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFFE8 [2025-09-21T08:11:38Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFFE9 [2025-09-21T08:11:38Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFFEA [2025-09-21T08:11:38Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFFEB [2025-09-21T08:11:38Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003A 00 [2025-09-21T08:11:38Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003B 00 [2025-09-21T08:11:38Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003C 00 [2025-09-21T08:11:38Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003D 00 [2025-09-21T08:11:38Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFFEC [2025-09-21T08:11:38Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFFED [2025-09-21T08:11:38Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFFEE [2025-09-21T08:11:38Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFFEF [2025-09-21T08:11:38Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003E 00 [2025-09-21T08:11:38Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003F 00 [2025-09-21T08:11:38Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80040 00 [2025-09-21T08:11:38Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80041 00 [2025-09-21T08:11:38Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80038 00 [2025-09-21T08:11:38Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80039 0B [2025-09-21T08:11:38Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFF7E [2025-09-21T08:11:38Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFF7F [2025-09-21T08:11:38Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFF80 [2025-09-21T08:11:38Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFF81 [2025-09-21T08:11:38Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80034 00 [2025-09-21T08:11:38Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80035 01 [2025-09-21T08:11:38Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80036 00 [2025-09-21T08:11:38Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80037 01 [2025-09-21T08:11:38Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80038 00 [2025-09-21T08:11:38Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80039 08 [2025-09-21T08:11:38Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003A FF [2025-09-21T08:11:38Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003B FF [2025-09-21T08:11:38Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003C FF [2025-09-21T08:11:38Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003D FF [2025-09-21T08:11:38Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003E FF [2025-09-21T08:11:38Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003F FF [2025-09-21T08:11:38Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80040 FF [2025-09-21T08:11:38Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80041 FF [2025-09-21T08:11:38Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80030 00 [2025-09-21T08:11:38Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80031 A4 [2025-09-21T08:11:38Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80032 01 [2025-09-21T08:11:38Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80033 80 [2025-09-21T08:11:38Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00FFFF50 00 [2025-09-21T08:11:38Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00FFFF51 00 [2025-09-21T08:11:38Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00FFFF52 09 [2025-09-21T08:11:38Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00FFFF53 98 [2025-09-21T08:11:38Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00FFFF54 00 [2025-09-21T08:11:38Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00FFFF55 1E [2025-09-21T08:11:38Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00FFFF56 00 [2025-09-21T08:11:38Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00FFFF57 00 [2025-09-21T08:11:38Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFF50 [2025-09-21T08:11:38Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFF51 [2025-09-21T08:11:38Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFF52 [2025-09-21T08:11:38Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFF53 [2025-09-21T08:11:38Z WARN snow_core::cpu_m68k::bus] Unaligned access: address 0000FFFF [2025-09-21T08:11:38Z DEBUG snow_core::cpu_m68k::cpu] Address error: read = true, address = 0000FFFF PC = 00408F70 [2025-09-21T08:11:38Z WARN snow_core::cpu_m68k::bus] Unaligned access: address 0000005B [2025-09-21T08:11:38Z DEBUG snow_core::cpu_m68k::cpu] Address error: read = true, address = 0000005B PC = 0040E450 [2025-09-21T08:11:38Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFFFE [2025-09-21T08:11:38Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFFFF [2025-09-21T08:11:38Z WARN snow_core::cpu_m68k::bus] Unaligned access: address 00FFFFFF [2025-09-21T08:11:38Z DEBUG snow_core::cpu_m68k::cpu] Address error: read = true, address = 00FFFFFF PC = 00FFFFFB [2025-09-21T08:11:38Z INFO single] Event: Status: EmulatorStatus { regs: RegisterFile { d: [0, 43690, 4194331, 81, 65535, 0, 0, 48], a: [2, 4236774, 4236870, 6, 4135084, 4178492, 4134688], usp: 0, isp: 4134570, sr: RegisterSR { 0: 8200, sr: 8200, ccr: 8, c: false, v: false, z: false, n: true, x: false, int_prio_mask: 0, m: false, supervisor: true, trace: false }, pc: 4236800, dfc: 0, sfc: 0, vbr: 0, caar: 0, cacr: RegisterCACR { 0: 0, e: false, f: false, ce: false, c: false }, msp: 0, fpu: FpuRegisterFile { fp: [Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }], fpcr: RegisterFPCR { 0: 0, mode: 0, rnd: 0, prec: 0, exc: FpuExceptions { 0: 0, inex1: false, inex2: false, dz: false, unfl: false, ovfl: false, operr: false, snan: false, bsun: false } }, fpsr: RegisterFPSR { 0: 0, fpcc: 0, fpcc_nan: false, fpcc_i: false, fpcc_z: false, fpcc_n: false, quotient: 0, quotient_s: false, exs: FpuExceptions { 0: 0, inex1: false, inex2: false, dz: false, unfl: false, ovfl: false, operr: false, snan: false, bsun: false }, aexc: FpuAccruedExceptions { 0: 0, inex: false, dz: false, unfl: false, ovfl: false, iop: false, snan: false, bsun: false } }, fpiar: 0 }, pmmu: PmmuRegisterFile { crp: RootPointerReg { 0: 0, lu: false, limit: 0, sg: false, dt: 0, table_addr: 0 }, srp: RootPointerReg { 0: 0, lu: false, limit: 0, sg: false, dt: 0, table_addr: 0 }, drp: RootPointerReg { 0: 0, lu: false, limit: 0, sg: false, dt: 0, table_addr: 0 }, pcsr: RegisterPCSR { 0: 0, ta: 0, flush: false, lw: false }, cal: AccessLevelReg { 0: 0, al: 0 }, val: AccessLevelReg { 0: 0, al: 0 }, scc: 0, ac: AccessControlReg { 0: 0, mc: false, alc: 0, mds: 0 }, tc: TcReg { 0: 0, enable: false, sre: false, fcl: false, ps: 0, is: 0, tia: 0, tib: 0, tic: 0, tid: 0 }, psr: RegisterPSR { 0: 0, bus_error: false, limit_violation: false, supervisor_violation: false, access_level_violatiom: false, write_protected: false, invalid: false, modified: false, gate: false, globally_shared: false, level_number: 0 }, last_desc: 0 } }, running: true, breakpoints: [], cycles: 277836396, fdd: [FddStatus { present: true, ejected: false, motor: true, writing: false, track: 66, image_title: "Dark Castle", dirty: false }, FddStatus { present: true, ejected: true, motor: false, writing: false, track: 4, image_title: "", dirty: false }, FddStatus { present: false, ejected: true, motor: false, writing: false, track: 4, image_title: "", dirty: false }], model: Plus, speed: Uncapped, scsi: [None, None, None, None, None, None, None] } [2025-09-21T08:11:38Z INFO single] Event: NextCode [2025-09-21T08:11:38Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFFE8 [2025-09-21T08:11:38Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFFE9 [2025-09-21T08:11:38Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFFEA [2025-09-21T08:11:38Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFFEB [2025-09-21T08:11:38Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003A 00 [2025-09-21T08:11:38Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003B 00 [2025-09-21T08:11:38Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003C 00 [2025-09-21T08:11:38Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003D 00 [2025-09-21T08:11:38Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFFEC [2025-09-21T08:11:38Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFFED [2025-09-21T08:11:38Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFFEE [2025-09-21T08:11:38Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFFEF [2025-09-21T08:11:38Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003E 00 [2025-09-21T08:11:38Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003F 00 [2025-09-21T08:11:38Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80040 00 [2025-09-21T08:11:38Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80041 00 [2025-09-21T08:11:38Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80038 00 [2025-09-21T08:11:38Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80039 0B [2025-09-21T08:11:38Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFF7E [2025-09-21T08:11:38Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFF7F [2025-09-21T08:11:38Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFF80 [2025-09-21T08:11:38Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFF81 [2025-09-21T08:11:38Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80034 00 [2025-09-21T08:11:38Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80035 01 [2025-09-21T08:11:38Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80036 00 [2025-09-21T08:11:38Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80037 01 [2025-09-21T08:11:38Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80038 00 [2025-09-21T08:11:38Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80039 08 [2025-09-21T08:11:38Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003A FF [2025-09-21T08:11:38Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003B FF [2025-09-21T08:11:38Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003C FF [2025-09-21T08:11:38Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003D FF [2025-09-21T08:11:38Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003E FF [2025-09-21T08:11:38Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003F FF [2025-09-21T08:11:38Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80040 FF [2025-09-21T08:11:38Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80041 FF [2025-09-21T08:11:38Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80030 00 [2025-09-21T08:11:38Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80031 A4 [2025-09-21T08:11:38Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80032 01 [2025-09-21T08:11:38Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80033 80 [2025-09-21T08:11:38Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00FFFF50 00 [2025-09-21T08:11:38Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00FFFF51 00 [2025-09-21T08:11:38Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00FFFF52 09 [2025-09-21T08:11:38Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00FFFF53 98 [2025-09-21T08:11:38Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00FFFF54 00 [2025-09-21T08:11:38Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00FFFF55 1E [2025-09-21T08:11:38Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00FFFF56 00 [2025-09-21T08:11:38Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00FFFF57 00 [2025-09-21T08:11:38Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFF50 [2025-09-21T08:11:38Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFF51 [2025-09-21T08:11:38Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFF52 [2025-09-21T08:11:38Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFF53 [2025-09-21T08:11:38Z WARN snow_core::cpu_m68k::bus] Unaligned access: address 0000FFFF [2025-09-21T08:11:38Z DEBUG snow_core::cpu_m68k::cpu] Address error: read = true, address = 0000FFFF PC = 00408F70 [2025-09-21T08:11:38Z WARN snow_core::cpu_m68k::bus] Unaligned access: address 0000005B [2025-09-21T08:11:38Z DEBUG snow_core::cpu_m68k::cpu] Address error: read = true, address = 0000005B PC = 0040E450 [2025-09-21T08:11:38Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFFFE [2025-09-21T08:11:38Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFFFF [2025-09-21T08:11:38Z WARN snow_core::cpu_m68k::bus] Unaligned access: address 00FFFFFF [2025-09-21T08:11:38Z DEBUG snow_core::cpu_m68k::cpu] Address error: read = true, address = 00FFFFFF PC = 00FFFFFB [2025-09-21T08:11:38Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFFE8 [2025-09-21T08:11:38Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFFE9 [2025-09-21T08:11:38Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFFEA [2025-09-21T08:11:38Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFFEB [2025-09-21T08:11:38Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003A 00 [2025-09-21T08:11:38Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003B 00 [2025-09-21T08:11:38Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003C 00 [2025-09-21T08:11:38Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003D 00 [2025-09-21T08:11:38Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFFEC [2025-09-21T08:11:38Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFFED [2025-09-21T08:11:38Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFFEE [2025-09-21T08:11:38Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFFEF [2025-09-21T08:11:38Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003E 00 [2025-09-21T08:11:38Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003F 00 [2025-09-21T08:11:38Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80040 00 [2025-09-21T08:11:38Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80041 00 [2025-09-21T08:11:38Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80038 00 [2025-09-21T08:11:38Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80039 0B [2025-09-21T08:11:38Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFF7E [2025-09-21T08:11:38Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFF7F [2025-09-21T08:11:38Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFF80 [2025-09-21T08:11:38Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFF81 [2025-09-21T08:11:38Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80034 00 [2025-09-21T08:11:38Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80035 01 [2025-09-21T08:11:38Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80036 00 [2025-09-21T08:11:38Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80037 01 [2025-09-21T08:11:38Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80038 00 [2025-09-21T08:11:38Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80039 08 [2025-09-21T08:11:38Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003A FF [2025-09-21T08:11:38Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003B FF [2025-09-21T08:11:38Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003C FF [2025-09-21T08:11:38Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003D FF [2025-09-21T08:11:38Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003E FF [2025-09-21T08:11:38Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003F FF [2025-09-21T08:11:38Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80040 FF [2025-09-21T08:11:38Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80041 FF [2025-09-21T08:11:38Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80030 00 [2025-09-21T08:11:38Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80031 A4 [2025-09-21T08:11:38Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80032 01 [2025-09-21T08:11:38Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80033 80 [2025-09-21T08:11:38Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00FFFF50 00 [2025-09-21T08:11:38Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00FFFF51 00 [2025-09-21T08:11:38Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00FFFF52 09 [2025-09-21T08:11:38Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00FFFF53 98 [2025-09-21T08:11:38Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00FFFF54 00 [2025-09-21T08:11:38Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00FFFF55 1E [2025-09-21T08:11:38Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00FFFF56 00 [2025-09-21T08:11:38Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00FFFF57 00 [2025-09-21T08:11:38Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFF50 [2025-09-21T08:11:38Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFF51 [2025-09-21T08:11:38Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFF52 [2025-09-21T08:11:38Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFF53 [2025-09-21T08:11:38Z WARN snow_core::cpu_m68k::bus] Unaligned access: address 0000FFFF [2025-09-21T08:11:38Z DEBUG snow_core::cpu_m68k::cpu] Address error: read = true, address = 0000FFFF PC = 00408F70 [2025-09-21T08:11:39Z INFO single] Event: Status: EmulatorStatus { regs: RegisterFile { d: [0, 0, 4194331, 50, 65535, 0, 0, 44], a: [2, 4236774, 4236870, 6, 4135458, 4180470, 4135062], usp: 0, isp: 4134940, sr: RegisterSR { 0: 8196, sr: 8196, ccr: 4, c: false, v: false, z: true, n: false, x: false, int_prio_mask: 0, m: false, supervisor: true, trace: false }, pc: 4236894, dfc: 0, sfc: 0, vbr: 0, caar: 0, cacr: RegisterCACR { 0: 0, e: false, f: false, ce: false, c: false }, msp: 0, fpu: FpuRegisterFile { fp: [Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }], fpcr: RegisterFPCR { 0: 0, mode: 0, rnd: 0, prec: 0, exc: FpuExceptions { 0: 0, inex1: false, inex2: false, dz: false, unfl: false, ovfl: false, operr: false, snan: false, bsun: false } }, fpsr: RegisterFPSR { 0: 0, fpcc: 0, fpcc_nan: false, fpcc_i: false, fpcc_z: false, fpcc_n: false, quotient: 0, quotient_s: false, exs: FpuExceptions { 0: 0, inex1: false, inex2: false, dz: false, unfl: false, ovfl: false, operr: false, snan: false, bsun: false }, aexc: FpuAccruedExceptions { 0: 0, inex: false, dz: false, unfl: false, ovfl: false, iop: false, snan: false, bsun: false } }, fpiar: 0 }, pmmu: PmmuRegisterFile { crp: RootPointerReg { 0: 0, lu: false, limit: 0, sg: false, dt: 0, table_addr: 0 }, srp: RootPointerReg { 0: 0, lu: false, limit: 0, sg: false, dt: 0, table_addr: 0 }, drp: RootPointerReg { 0: 0, lu: false, limit: 0, sg: false, dt: 0, table_addr: 0 }, pcsr: RegisterPCSR { 0: 0, ta: 0, flush: false, lw: false }, cal: AccessLevelReg { 0: 0, al: 0 }, val: AccessLevelReg { 0: 0, al: 0 }, scc: 0, ac: AccessControlReg { 0: 0, mc: false, alc: 0, mds: 0 }, tc: TcReg { 0: 0, enable: false, sre: false, fcl: false, ps: 0, is: 0, tia: 0, tib: 0, tic: 0, tid: 0 }, psr: RegisterPSR { 0: 0, bus_error: false, limit_violation: false, supervisor_violation: false, access_level_violatiom: false, write_protected: false, invalid: false, modified: false, gate: false, globally_shared: false, level_number: 0 }, last_desc: 0 } }, running: true, breakpoints: [], cycles: 282020012, fdd: [FddStatus { present: true, ejected: false, motor: true, writing: false, track: 66, image_title: "Dark Castle", dirty: false }, FddStatus { present: true, ejected: true, motor: false, writing: false, track: 4, image_title: "", dirty: false }, FddStatus { present: false, ejected: true, motor: false, writing: false, track: 4, image_title: "", dirty: false }], model: Plus, speed: Uncapped, scsi: [None, None, None, None, None, None, None] } [2025-09-21T08:11:39Z INFO single] Event: NextCode [2025-09-21T08:11:39Z WARN snow_core::cpu_m68k::bus] Unaligned access: address 0000005B [2025-09-21T08:11:39Z DEBUG snow_core::cpu_m68k::cpu] Address error: read = true, address = 0000005B PC = 0040E450 [2025-09-21T08:11:39Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFFFE [2025-09-21T08:11:39Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFFFF [2025-09-21T08:11:39Z WARN snow_core::cpu_m68k::bus] Unaligned access: address 00FFFFFF [2025-09-21T08:11:39Z DEBUG snow_core::cpu_m68k::cpu] Address error: read = true, address = 00FFFFFF PC = 00FFFFFB [2025-09-21T08:11:39Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFFE8 [2025-09-21T08:11:39Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFFE9 [2025-09-21T08:11:39Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFFEA [2025-09-21T08:11:39Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFFEB [2025-09-21T08:11:39Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003A 00 [2025-09-21T08:11:39Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003B 00 [2025-09-21T08:11:39Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003C 00 [2025-09-21T08:11:39Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003D 00 [2025-09-21T08:11:39Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFFEC [2025-09-21T08:11:39Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFFED [2025-09-21T08:11:39Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFFEE [2025-09-21T08:11:39Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFFEF [2025-09-21T08:11:39Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003E 00 [2025-09-21T08:11:39Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003F 00 [2025-09-21T08:11:39Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80040 00 [2025-09-21T08:11:39Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80041 00 [2025-09-21T08:11:39Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80038 00 [2025-09-21T08:11:39Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80039 0B [2025-09-21T08:11:39Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFF7E [2025-09-21T08:11:39Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFF7F [2025-09-21T08:11:39Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFF80 [2025-09-21T08:11:39Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFF81 [2025-09-21T08:11:39Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80034 00 [2025-09-21T08:11:39Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80035 01 [2025-09-21T08:11:39Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80036 00 [2025-09-21T08:11:39Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80037 01 [2025-09-21T08:11:39Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80038 00 [2025-09-21T08:11:39Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80039 08 [2025-09-21T08:11:39Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003A FF [2025-09-21T08:11:39Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003B FF [2025-09-21T08:11:39Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003C FF [2025-09-21T08:11:39Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003D FF [2025-09-21T08:11:39Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003E FF [2025-09-21T08:11:39Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003F FF [2025-09-21T08:11:39Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80040 FF [2025-09-21T08:11:39Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80041 FF [2025-09-21T08:11:39Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80030 00 [2025-09-21T08:11:39Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80031 A4 [2025-09-21T08:11:39Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80032 01 [2025-09-21T08:11:39Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80033 80 [2025-09-21T08:11:39Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00FFFF50 00 [2025-09-21T08:11:39Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00FFFF51 00 [2025-09-21T08:11:39Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00FFFF52 09 [2025-09-21T08:11:39Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00FFFF53 98 [2025-09-21T08:11:39Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00FFFF54 00 [2025-09-21T08:11:39Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00FFFF55 1E [2025-09-21T08:11:39Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00FFFF56 00 [2025-09-21T08:11:39Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00FFFF57 00 [2025-09-21T08:11:39Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFF50 [2025-09-21T08:11:39Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFF51 [2025-09-21T08:11:39Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFF52 [2025-09-21T08:11:39Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFF53 [2025-09-21T08:11:39Z WARN snow_core::cpu_m68k::bus] Unaligned access: address 0000FFFF [2025-09-21T08:11:39Z DEBUG snow_core::cpu_m68k::cpu] Address error: read = true, address = 0000FFFF PC = 00408F70 [2025-09-21T08:11:39Z WARN snow_core::cpu_m68k::bus] Unaligned access: address 0000005B [2025-09-21T08:11:39Z DEBUG snow_core::cpu_m68k::cpu] Address error: read = true, address = 0000005B PC = 0040E450 [2025-09-21T08:11:39Z INFO single] Event: Status: EmulatorStatus { regs: RegisterFile { d: [16, 0, 4194331, 5, 65535, 0, 0, 32], a: [4204004, 15720958, 4236870, 6, 4135036, 4183346, 4134640], usp: 0, isp: 4134476, sr: RegisterSR { 0: 8464, sr: 8464, ccr: 16, c: false, v: false, z: false, n: false, x: true, int_prio_mask: 1, m: false, supervisor: true, trace: false }, pc: 4204018, dfc: 0, sfc: 0, vbr: 0, caar: 0, cacr: RegisterCACR { 0: 0, e: false, f: false, ce: false, c: false }, msp: 0, fpu: FpuRegisterFile { fp: [Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }], fpcr: RegisterFPCR { 0: 0, mode: 0, rnd: 0, prec: 0, exc: FpuExceptions { 0: 0, inex1: false, inex2: false, dz: false, unfl: false, ovfl: false, operr: false, snan: false, bsun: false } }, fpsr: RegisterFPSR { 0: 0, fpcc: 0, fpcc_nan: false, fpcc_i: false, fpcc_z: false, fpcc_n: false, quotient: 0, quotient_s: false, exs: FpuExceptions { 0: 0, inex1: false, inex2: false, dz: false, unfl: false, ovfl: false, operr: false, snan: false, bsun: false }, aexc: FpuAccruedExceptions { 0: 0, inex: false, dz: false, unfl: false, ovfl: false, iop: false, snan: false, bsun: false } }, fpiar: 0 }, pmmu: PmmuRegisterFile { crp: RootPointerReg { 0: 0, lu: false, limit: 0, sg: false, dt: 0, table_addr: 0 }, srp: RootPointerReg { 0: 0, lu: false, limit: 0, sg: false, dt: 0, table_addr: 0 }, drp: RootPointerReg { 0: 0, lu: false, limit: 0, sg: false, dt: 0, table_addr: 0 }, pcsr: RegisterPCSR { 0: 0, ta: 0, flush: false, lw: false }, cal: AccessLevelReg { 0: 0, al: 0 }, val: AccessLevelReg { 0: 0, al: 0 }, scc: 0, ac: AccessControlReg { 0: 0, mc: false, alc: 0, mds: 0 }, tc: TcReg { 0: 0, enable: false, sre: false, fcl: false, ps: 0, is: 0, tia: 0, tib: 0, tic: 0, tid: 0 }, psr: RegisterPSR { 0: 0, bus_error: false, limit_violation: false, supervisor_violation: false, access_level_violatiom: false, write_protected: false, invalid: false, modified: false, gate: false, globally_shared: false, level_number: 0 }, last_desc: 0 } }, running: true, breakpoints: [], cycles: 285685128, fdd: [FddStatus { present: true, ejected: false, motor: true, writing: false, track: 66, image_title: "Dark Castle", dirty: false }, FddStatus { present: true, ejected: true, motor: false, writing: false, track: 4, image_title: "", dirty: false }, FddStatus { present: false, ejected: true, motor: false, writing: false, track: 4, image_title: "", dirty: false }], model: Plus, speed: Uncapped, scsi: [None, None, None, None, None, None, None] } [2025-09-21T08:11:39Z INFO single] Event: NextCode [2025-09-21T08:11:39Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFFFE [2025-09-21T08:11:39Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFFFF [2025-09-21T08:11:39Z WARN snow_core::cpu_m68k::bus] Unaligned access: address 00FFFFFF [2025-09-21T08:11:39Z DEBUG snow_core::cpu_m68k::cpu] Address error: read = true, address = 00FFFFFF PC = 00FFFFFB [2025-09-21T08:11:39Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFFE8 [2025-09-21T08:11:39Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFFE9 [2025-09-21T08:11:39Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFFEA [2025-09-21T08:11:39Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFFEB [2025-09-21T08:11:39Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003A 00 [2025-09-21T08:11:39Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003B 00 [2025-09-21T08:11:39Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003C 00 [2025-09-21T08:11:39Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003D 00 [2025-09-21T08:11:39Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFFEC [2025-09-21T08:11:39Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFFED [2025-09-21T08:11:39Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFFEE [2025-09-21T08:11:39Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFFEF [2025-09-21T08:11:39Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003E 00 [2025-09-21T08:11:39Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003F 00 [2025-09-21T08:11:39Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80040 00 [2025-09-21T08:11:39Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80041 00 [2025-09-21T08:11:39Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80038 00 [2025-09-21T08:11:39Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80039 0B [2025-09-21T08:11:39Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFF7E [2025-09-21T08:11:39Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFF7F [2025-09-21T08:11:39Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFF80 [2025-09-21T08:11:39Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFF81 [2025-09-21T08:11:39Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80034 00 [2025-09-21T08:11:39Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80035 01 [2025-09-21T08:11:39Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80036 00 [2025-09-21T08:11:39Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80037 01 [2025-09-21T08:11:39Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80038 00 [2025-09-21T08:11:39Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80039 08 [2025-09-21T08:11:39Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003A FF [2025-09-21T08:11:39Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003B FF [2025-09-21T08:11:39Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003C FF [2025-09-21T08:11:39Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003D FF [2025-09-21T08:11:39Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003E FF [2025-09-21T08:11:39Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003F FF [2025-09-21T08:11:39Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80040 FF [2025-09-21T08:11:39Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80041 FF [2025-09-21T08:11:39Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80030 00 [2025-09-21T08:11:39Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80031 A4 [2025-09-21T08:11:39Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80032 01 [2025-09-21T08:11:39Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80033 80 [2025-09-21T08:11:39Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00FFFF50 00 [2025-09-21T08:11:39Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00FFFF51 00 [2025-09-21T08:11:39Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00FFFF52 09 [2025-09-21T08:11:39Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00FFFF53 98 [2025-09-21T08:11:39Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00FFFF54 00 [2025-09-21T08:11:39Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00FFFF55 1E [2025-09-21T08:11:39Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00FFFF56 00 [2025-09-21T08:11:39Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00FFFF57 00 [2025-09-21T08:11:39Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFF50 [2025-09-21T08:11:39Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFF51 [2025-09-21T08:11:39Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFF52 [2025-09-21T08:11:39Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFF53 [2025-09-21T08:11:39Z WARN snow_core::cpu_m68k::bus] Unaligned access: address 0000FFFF [2025-09-21T08:11:39Z DEBUG snow_core::cpu_m68k::cpu] Address error: read = true, address = 0000FFFF PC = 00408F70 [2025-09-21T08:11:39Z WARN snow_core::cpu_m68k::bus] Unaligned access: address 0000005B [2025-09-21T08:11:39Z DEBUG snow_core::cpu_m68k::cpu] Address error: read = true, address = 0000005B PC = 0040E450 [2025-09-21T08:11:39Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFFFE [2025-09-21T08:11:39Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFFFF [2025-09-21T08:11:39Z WARN snow_core::cpu_m68k::bus] Unaligned access: address 00FFFFFF [2025-09-21T08:11:39Z DEBUG snow_core::cpu_m68k::cpu] Address error: read = true, address = 00FFFFFF PC = 00FFFFFB [2025-09-21T08:11:39Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFFE8 [2025-09-21T08:11:39Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFFE9 [2025-09-21T08:11:39Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFFEA [2025-09-21T08:11:39Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFFEB [2025-09-21T08:11:39Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003A 00 [2025-09-21T08:11:39Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003B 00 [2025-09-21T08:11:39Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003C 00 [2025-09-21T08:11:39Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003D 00 [2025-09-21T08:11:39Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFFEC [2025-09-21T08:11:39Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFFED [2025-09-21T08:11:39Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFFEE [2025-09-21T08:11:39Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFFEF [2025-09-21T08:11:39Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003E 00 [2025-09-21T08:11:39Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003F 00 [2025-09-21T08:11:39Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80040 00 [2025-09-21T08:11:39Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80041 00 [2025-09-21T08:11:39Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80038 00 [2025-09-21T08:11:39Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80039 0B [2025-09-21T08:11:39Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFF7E [2025-09-21T08:11:39Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFF7F [2025-09-21T08:11:39Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFF80 [2025-09-21T08:11:39Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFF81 [2025-09-21T08:11:39Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80034 00 [2025-09-21T08:11:39Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80035 01 [2025-09-21T08:11:39Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80036 00 [2025-09-21T08:11:39Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80037 01 [2025-09-21T08:11:39Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80038 00 [2025-09-21T08:11:39Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80039 08 [2025-09-21T08:11:39Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003A FF [2025-09-21T08:11:39Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003B FF [2025-09-21T08:11:39Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003C FF [2025-09-21T08:11:39Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003D FF [2025-09-21T08:11:39Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003E FF [2025-09-21T08:11:39Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F8003F FF [2025-09-21T08:11:39Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80040 FF [2025-09-21T08:11:39Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80041 FF [2025-09-21T08:11:39Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80030 00 [2025-09-21T08:11:39Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80031 A4 [2025-09-21T08:11:39Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80032 01 [2025-09-21T08:11:39Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00F80033 80 [2025-09-21T08:11:39Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00FFFF50 00 [2025-09-21T08:11:39Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00FFFF51 00 [2025-09-21T08:11:39Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00FFFF52 09 [2025-09-21T08:11:39Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00FFFF53 98 [2025-09-21T08:11:39Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00FFFF54 00 [2025-09-21T08:11:39Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00FFFF55 1E [2025-09-21T08:11:39Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00FFFF56 00 [2025-09-21T08:11:39Z WARN snow_core::mac::compact::bus] Write to unimplemented address: 00FFFF57 00 [2025-09-21T08:11:39Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFF50 [2025-09-21T08:11:39Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFF51 [2025-09-21T08:11:39Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFF52 [2025-09-21T08:11:39Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFF53 [2025-09-21T08:11:39Z WARN snow_core::cpu_m68k::bus] Unaligned access: address 0000FFFF [2025-09-21T08:11:39Z DEBUG snow_core::cpu_m68k::cpu] Address error: read = true, address = 0000FFFF PC = 00408F70 [2025-09-21T08:11:40Z INFO single] Event: Status: EmulatorStatus { regs: RegisterFile { d: [0, 0, 4194331, 73, 65535, 0, 0, 16], a: [2, 4236774, 4236870, 6, 4134782, 4178970, 4134386], usp: 0, isp: 4134264, sr: RegisterSR { 0: 8196, sr: 8196, ccr: 4, c: false, v: false, z: true, n: false, x: false, int_prio_mask: 0, m: false, supervisor: true, trace: false }, pc: 4236880, dfc: 0, sfc: 0, vbr: 0, caar: 0, cacr: RegisterCACR { 0: 0, e: false, f: false, ce: false, c: false }, msp: 0, fpu: FpuRegisterFile { fp: [Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }, Float { sem: Semantics { exponent: 15, precision: 64, mode: NearestTiesToEven }, sign: false, exp: 0, mantissa: BigInt { parts: [0] }, category: NaN }], fpcr: RegisterFPCR { 0: 0, mode: 0, rnd: 0, prec: 0, exc: FpuExceptions { 0: 0, inex1: false, inex2: false, dz: false, unfl: false, ovfl: false, operr: false, snan: false, bsun: false } }, fpsr: RegisterFPSR { 0: 0, fpcc: 0, fpcc_nan: false, fpcc_i: false, fpcc_z: false, fpcc_n: false, quotient: 0, quotient_s: false, exs: FpuExceptions { 0: 0, inex1: false, inex2: false, dz: false, unfl: false, ovfl: false, operr: false, snan: false, bsun: false }, aexc: FpuAccruedExceptions { 0: 0, inex: false, dz: false, unfl: false, ovfl: false, iop: false, snan: false, bsun: false } }, fpiar: 0 }, pmmu: PmmuRegisterFile { crp: RootPointerReg { 0: 0, lu: false, limit: 0, sg: false, dt: 0, table_addr: 0 }, srp: RootPointerReg { 0: 0, lu: false, limit: 0, sg: false, dt: 0, table_addr: 0 }, drp: RootPointerReg { 0: 0, lu: false, limit: 0, sg: false, dt: 0, table_addr: 0 }, pcsr: RegisterPCSR { 0: 0, ta: 0, flush: false, lw: false }, cal: AccessLevelReg { 0: 0, al: 0 }, val: AccessLevelReg { 0: 0, al: 0 }, scc: 0, ac: AccessControlReg { 0: 0, mc: false, alc: 0, mds: 0 }, tc: TcReg { 0: 0, enable: false, sre: false, fcl: false, ps: 0, is: 0, tia: 0, tib: 0, tic: 0, tid: 0 }, psr: RegisterPSR { 0: 0, bus_error: false, limit_violation: false, supervisor_violation: false, access_level_violatiom: false, write_protected: false, invalid: false, modified: false, gate: false, globally_shared: false, level_number: 0 }, last_desc: 0 } }, running: true, breakpoints: [], cycles: 290083836, fdd: [FddStatus { present: true, ejected: false, motor: true, writing: false, track: 66, image_title: "Dark Castle", dirty: false }, FddStatus { present: true, ejected: true, motor: false, writing: false, track: 4, image_title: "", dirty: false }, FddStatus { present: false, ejected: true, motor: false, writing: false, track: 4, image_title: "", dirty: false }], model: Plus, speed: Uncapped, scsi: [None, None, None, None, None, None, None] } [2025-09-21T08:11:40Z INFO single] Event: NextCode [2025-09-21T08:11:40Z WARN snow_core::cpu_m68k::bus] Unaligned access: address 0000005B [2025-09-21T08:11:40Z DEBUG snow_core::cpu_m68k::cpu] Address error: read = true, address = 0000005B PC = 0040E450 [2025-09-21T08:11:40Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFFFE [2025-09-21T08:11:40Z WARN snow_core::mac::compact::bus] Read from unimplemented address: 00FFFFFF [2025-09-21T08:11:40Z WARN snow_core::cpu_m68k::bus] Unaligned access: address 00FFFFFF [2025-09-21T08:11:40Z DEBUG snow_core::cpu_m68k::cpu] Address error: read = true, address = 00FFFFFF PC = 00FFFFFB [2025-09-21T08:11:41Z INFO single] deduplicated 120 frames to 120